• I have an Arm 32-bit Cortex V3.10, Does anyone know the manufacturer/email?

    jeff
    jeff

    I need a configuration to get rid of the spacing between the numbers in a single barcode.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Bootloader. VTOR, BOOTPROT FUSE, JUMP to app and other related questions

    Iván
    Iván

    Hello everyone!

    I am writing here because I am having some issues developing my own bootloader. I am currently working with an ATMEL SAM R21 which has an ARM CORTEX M0+ in it.

    Firstly I am going to summarize the more relevant points (or I think those are…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Is ARMv7-M3 thumb instructions compatible to ARMv7-A thumb?

    Kaiyuan
    Kaiyuan

    Hello guys,

    I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA.

    Is ARMv7-M3 instructions compatible to ARMv7-A, especially thumb instructions?

    Thank you very much.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • lpc2148  library  bundles and c programming tutorial

    Gokhu
    Gokhu

    Hi Friends.. I am Gokhu..New to ARM..i start my learning process..i need library function of iolpc2148.h and main.h and stdio.h, RTC.h,ADC.h and DAC.h uart.h these kind of library bundle and i need a material or online site to learn arm C programming…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M7 irq enable/disable

    Valentin
    Valentin

    In the appnote "ARM Cortex-M Programming Guide to Memory Barrier Instructions" there is a section that describes the use of memory barriers in the Cortex-M processors on a case-by-case basis.

    Are those cases relevant for the Cortex M7 - especially…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Use of SV Call & NMI Exceptions in ARM

    Arun
    Arun

    What is the use or application of SV Call and NMI Exception in ARM Cortex M0 .

    Is it someway related to RTOS?, if so , how?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Interruptible-restartable instructions and Others

    Kilian Timmler
    Kilian Timmler

    Hi,

    As I have found in:

    Cortex-M0+ Devices Generic User Guide: 2.1.3. Core registers

    There is information about instruction behaviour during interrupts:

    "Interruptible-restartable instructions

    The interruptible-restartable instructions are LDM, STM,…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Race condition between wake up event and WFI on Cortex-M3/M4

    neo
    neo

    When I read below thread in arm forum, I still not clear which one is the safety way.

    Cortex-M4: guaranteed wakeup from WFI?

    There're two solutions mentioned above, using WFE instead of WFI, and swap __WFI() and __enable_irq().

    I can understand WFE…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • CAN Stack Integration for ARM cortex R5F

    Prateek Nandi
    Prateek Nandi

    Hello All,

    I am integrating CAN stack, on Spansion S6J3xx series.

    I have configured Main clock as Input frequency, configured CAN transceiver IC and called CclPowerOnInit().

    Now calling CanTransmit(X_TxHandle), function in a 100ms task, but still no signal…

    • over 4 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • How to prepare ADC data for Q31_t CMSIS DSP functions?

    Andrea Bettati
    Andrea Bettati

    Hi to you all,
    I've another post on the forum (here's the link Process ADC data, moved by DMA, using CMSIS DSP: what's the right way? ), but since I think I made some small steps forward I felt I could be a little more specific. I hope this…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Snake robot with ARM Cortex-M4 processor

    Prashant.Sulakhe
    Prashant.Sulakhe

    I want to design an snake robot with ARM Cortex-M4 processor can u help how to start? please help me.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Are there any ARM processors with hardware H.264 encoder?

    ENRICO
    ENRICO

    Hi,

    I'm looking for and ARM processor with an hardware H.264 encoder.

    The production volume is 5000 boards a year.

    The product will be ready in the Q1 of 2017 therefore I can evaluate also microprocessor in a preview status.

    Thanks for any help,

    Enrico…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Loss of information - SMMUL

    Petr
    Petr

    Why the Cortex M4 instruction SMMUL (32 = 32 x 32b) preserves a redundant sign bit and discards one useful bit of information? What could possibly be the justification for such blatant disregard of the ISO/IEC TR 18037 standard Fract format?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Process ADC data, moved by DMA, using CMSIS DSP: what's the right way?

    Andrea Bettati
    Andrea Bettati

    Hi to you all,
    I've a firmware running on a NXP LPCLink2 (LPC4370: 204 Mhz Cortex M4 MCU) board which basically does this:

    • Fills the ADC FIFO @40msps.
    • Copies the data into memory using the built-in DMA Controller and 2 linked buffers.
    • Processes one buffer…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Parallelism between CPU and FPU

    Matic
    Matic

    Hi.

    I have a question regarding Cortex-M4 processor with floating point unit. Is it somehow possible to do some computation in parallel in CPU (with integers) and FPU (with floats)?

    Probably not, because both units need their own instructions to perform…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Can we Modify the Flash Memory Access Permission with MPU( Memory Protection Unit)

    harshan
    harshan

    Hi Sir,

             Can i change Flash Memory Permission through MPU??

    Thanks and Regards,
    Harshan.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • in arm7tdmi, when FIQ and RIQ occures at same time so how both are executed sequentially,first FIQ and thenIRQ?

    nirav
    nirav

    in arm7tdmi, suppose instruction is being executed and at same time FIQ and IRQ both occur  at same time.now according to priority FIQ will be handled then IRQ  but my question is that how it will handled IRQ after  return from FIQ

    i means…

    • Answered
    • over 4 years ago
    • Processors
    • Classic processors forum
  • Alignment in ARM?

    Natesh Raina
    Natesh Raina

    I could not clearly understand the alignment issues present in ARM. Sometimes I get BUS ERROR while running an assembly file but don't know how to resolve it. Some of the doubts:

    1. Is it better to store registers pairwise or individually on the stack…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • VTOR: offset address configuration

    Katsuhiro Atsumi
    Katsuhiro Atsumi

    Core: Cortex-M4F

    Do I need to configure vector table offset address to 0xnnnn_n000?

    In case of 0x3080(Flash region), the program jump to unexpected code.

    I think it is caused by mismatching between vector number and handler address.

    In case of 0x3000(Flash…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Usefulness of MPU in a non-OS system

    Matic
    Matic

    Hi.

    We are developing a product which has to achieve some safety requirements. The system is quite simple, non-OS, running in a Privileged mode only on a Cortex-M4. I would like to implement a Memory Protection Unit somehow. Could you please give any advice…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Memory protection unit - Cortex-M4

    Matic
    Matic

    Hi.

    I am writing back regarding MPU usage. I implemented it into the software in next ways (note, that program is quite simple - only privileged mode, no RTOS):

    1. I enabled background region, thus all addressable memory is fully accessible, unless there…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • maximum level of functions than can be called within

    NABEEN LAL AMATYA
    NABEEN LAL AMATYA

    function1 calling function2, function2 calling function3, function3 calling function4 and so on.

    Maximum stage depends upon Stack Size, right? How to identify Stack Size and if required how to change it? I am using IAR and Fujitsu ARM Cortex M3 MB9AF312K…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Hard Fault in cortex m4

    hemant
    hemant

    Hello All,

    Good Morning!

    I am working on Cortex m4.

    I have read following about hard fault ,

    "Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Warning: It blocks containing 32-bit Thumb instructions are deprecated in ARMv8 with GCC 4.9

    Carlos Delfino
    Carlos Delfino

    Dear colleagues.

    I am compiling the Intel TBB in an effort to optimize my code to the Cortex-M53, however, because I was still forced to use GCC 4.9 I'm getting some warning messages about the use of  32bit Thumb Instrucions in IT blocks:

    Warning…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Guidelines on reducing Cache Miss rate

    techguyz
    techguyz

    Hi Experts,

    Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ?

    If it is more specific to A/R/M then its great..

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • View related content from anywhere
  • More
  • Cancel
<>