• 【Cortex-M4 with STM32F412RG】

    Kieron Kotaroh Nakamura
    Kieron Kotaroh Nakamura

    I am now composing functions to wake up Cortex-M4 with STM32F412RG embedded on Arduino using timers after making Cortex-M4 deep sleep mode.

    In realising the functionality above, peripheral clocks should be operated by some sources, Since deep sleep mode…

    • Answered
    • 5 days ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M3 DesignStart FPGA-Xilinx edition package bitstream incompatible on Arty A7-100T

    Shiping
    Shiping

    Hi, there

    I just downloaded  the "Cortex-M3 DesignStart  FPGA-Xilinx edition packag" and tried to load the bitstream up to Arty A7-100T , but got error

    "Incorrect bitstream assigned to device. Bitfile is incompatible for this device"…

    • 9 days ago
    • Processors
    • Cortex-M / M-Profile forum
  • External Private Peripheral Bus

    Mahdi Masoudi
    Mahdi Masoudi

    Hi!

    What is exact differences between IPPB (Internal Private Peripheral Bus) and EPPB (External Private Peripheral Bus)?

    I think that IPPB peripherals and components are inside the processor (Cortex-M3/M4 core etc.) but, the EPPB peripherals and components…

    • 1 month ago
    • Processors
    • Cortex-M / M-Profile forum
  • Microcontroller selection - Requirements and question in description

    SaiG
    SaiG

    Hello Everyone, 

    I am trying to build a device that displays images or videos sent by a smartphone via bluetooth onto an LCD screen. However, I am not thinking about streaming the content in any way, but rather thinking about storing the images/videos…

    • 1 month ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M3 bare metal start_up example error in clock ticks

    dak.sera
    dak.sera

    Hi,

    the bare metal example code in ARM ds giving me mismatched output on clock ticks. debug output is given here.

    Cortex-M3 bare-metal startup example
    Insertion sort took 1 clock ticks
    Shell sort took 0 clock ticks
    Quick sort took 0 clock ticks
    SysTick interrupt…

    • 2 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Compiling libgcc not optimized

    EnricoTabanelli
    EnricoTabanelli

    Good moorning,

    I am trying to compile libgcc for arm-none-eabi target from scratch, since I need to compare Floating Point SW emulation on an ARM Cortex-M4 and Risc-V based processors. The problem is that by default GCC includes the optimized version…

    • 3 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Timer not working in stm32f401re

    Ashk.tr
    Ashk.tr

    i want to setup timer in STM32F401RE and i already have this code:


    int main(void) {
    TIM1_init();

    while (1) {}
    }


    /// initialize TIM1
    /// timer TIM1 channel 2 is configed to generate PWM at 1kHz. the output of the
    void TIM1_init(void) {
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;…
    • 3 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • What will be the reason for MDR register not getting updated??

    omkardixi
    omkardixi

    I'm trying I2C while debugging i found that the I2CMDR register is not updating I'm uploading screenshots below.

    • 5 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Understanding interrupt latency and jitter in Cortex-M

    Simen Sørensen
    Simen Sørensen

    Hi,

    I've been trying to get a good grasp of the variables associated with interrupt handling in the Cortex-M family. I've read "A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the Arm Cortex-M processors" and "…

    • Answered
    • 7 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Porting C code (using intrinsics) from Cortex-M to Cortex-A?

    DanijelDomazet
    DanijelDomazet

    Hi, I am looking at ARM CMSIS code for biquad float32 implementation. This is written for Cortex-M as documentation states. How much effort would be needed to port this code to Cortex-A53? The code should be fast, optimized using intrinsics, not assembly…

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • How is it possible to integrated/interfaced RTOS into ARM -Mx series ?

    Himal Subedi
    Himal Subedi

    Guten tag, 

    I am currently been keen focus on interfacing RTOS in ARM cortex Mx series. With ARM nomenclature, the Cortex-Mx series is designed for Hard-Realtime applications. Properties like low interrupt latency, few pipelines, no cache, no MMU make it…

    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Introducing Arm’s AI Virtual Tech Sessions for Software Developers

    Mary Bennion
    Mary Bennion

    Turn back the clocks three months and the events industry was in turmoil. Leading industry events across the globe were being canceled or scaled-down significantly, and the next opportunity of a face-to-face event was very uncertain. But now, our industry…

    • 8 months ago
    • Processors
    • Machine Learning IP blog
  • How to write to DHCSR register in Cortex-M

    shincm
    shincm

    I want to make C_DEBUGEN (register DHCSR) zero.

    I tried this. (CoreDebug->DHCSR = (unsigned int)0xA05F0000;) 

    But again, C_Debugen is set to 1.

    I want to know how to set it to 0.

    It is possible to force change using T32, but is it possible in code?

    …
    • 9 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Example of what happpens inside the Cortex-M 4

    Frederikke Kold
    Frederikke Kold

    Hello i am a student at cphbusiness in Denmark, and i am currently doing a research project on the Cortex-m 4. 
    i am hoping someone can help me understand what exactly is going on inside the processor. I have attached a picture, and i am hoping someone…

    • 9 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • STM32H745 dual-core debugging with IAR toolchain

    madhan719
    madhan719

    Hi All!

     

    I am working on STM32H745 dual-core controller and IAR Embedded Workbench for ARM toolchain V8.40.1 for development.

    I have completed all my work on individual core test and debugging with help of ST-Link V3 as debugger but unfortunately, I am…

    • 9 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Hard fault in STM32F101RF due to MRC2 Disassembly ??!!

    Vish_
    Vish_

    Hi all,

    I am having a bootloader code wherein I will sending/receiving data via USART . I have configured USART to operate in interrupt mode.

    USART functionality works perfectly fine independently. Verified this with multiple read/write instances.

    When…

    • 10 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR)

    schroedingers_katze
    schroedingers_katze

    I am trying to find the location of the register where the timestamp generator can be enabled on a Cortex-M4 processor.

    In the CoreSight SoC Technical Reference Manual on page 3-210 it is mentioned that the register (CNTCR) is in the PSELCTRL region…

    • Answered
    • 11 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Arm Cortex-M55 and Ethos-U55 Processors: Extending the Performance of Arm’s ML Portfolio for Endpoint Devices

    Thomas Lorenser
    Thomas Lorenser

    The advent of artificial intelligence (AI) is creating a wealth of opportunities ranging from better user experiences with consumer products to automated quality control on factory floors – and this list of AI-driven use-cases is growing exponentially…

    • over 1 year ago
    • Processors
    • Processors blog
  • Debugger-based Firmware Test Framework

    tomonarm
    tomonarm

    Hi all.

     

    I'm currently working on a Python-based framework for on-target firmware testing of firmware of Cortex-M MCU systems. The approach is heavily based on the use of the debug probe to perform unit as well as system tests.

    The framework I have…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • When does a Cortex Mx wake up from "wfi" ? Is it configurable?

    d.ry
    d.ry

    Hello,

    Question about the "hint" instruction  - WFI.

    The armv7m arch manual (i'm using DDI0403_B, latest?) says it will come out of the suspended / low-power state if:

    • A reset.
    • An asynchronous exception at a priority that, if PRIMASK…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M MPU User access to privileged code

    Ian Taig
    Ian Taig

    Hi All,

    I currently want to make use of the MPU. I have several functions which are required to be in privileged mode and are stored in a region set as privileged-read-only, user denied, executable.

    This works fine when a BL or BLX instruction jumps here…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to detect FPU in Cortex M?

    mastupristi
    mastupristi

    Cortex-M processors implement the CPUID register, through which it is possible to detect information about the core: part number (e.g. Cortex M7 or M4), revision and patch level (e.g. r1p2), etc.

    Is there a register or a way to detect if the FPU has been…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARM Cortex-M3 floating point...

    dtvonly dtvonly
    dtvonly dtvonly
    Note: This was originally posted on 9th May 2008 at http://forums.arm.com

    Hi.  Are there any floating point support for the ARM CORTEX-M3?
    • over 7 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Abort some questions of arm interrupt

    josh zhao
    josh zhao
    Note: This was originally posted on 20th June 2008 at http://forums.arm.com

    I try to understand arm interrupt,there are some questions I don't know,
      1.   Why the nested interrupt has to switch out of irq mode to svc mode?  I think  it only pushes…
    • over 7 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Loading instruction set

    chaitanya chaitanya
    chaitanya chaitanya
    Note: This was originally posted on 7th October 2008 at http://forums.arm.com

    HI,
       I am trying out the Cortex M1 on an altera FPGA. I have an example implementation from the Altera kit which uses ITCM to load the software files on the ARM. I want to instead…
    • over 7 years ago
    • Processors
    • Cortex-M / M-Profile forum
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