• Compute the division via shift instruction

    gapry
    gapry

    I write the code as following to evaluate the expression n = n / 2

    asrs r0, r0, #1

    But, I found the GCC will translate the expression n = n / 2 into the following instruction

    lsrs r1, r0, #31                                                                             

    adds r0, r1, r0

    asrs r0, r0, #1

    Why does it need to add the…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How long are the Cortex-M7 pipeline stages?

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,

    recently ARM updated the Cortex-M7 information.

    I think the biggest topic would be that the pipeline details were opened.

    The new information says that the integer pipeline is 4 stage and the floating point pipeline is 5 stage.

    However, the…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • White Paper Document on Selection of Processors

    techguyz
    techguyz

    Hi Experts,

    As the general discussions seen in the community, it would be great if there is a general guidelines on the list of criteria or guidelines involved in the selection of Cortex A/R/M series Processors ?

    Rather than application specific some other…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Break Points and Watch Points

    harshan
    harshan

    Greetings,

                   Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Get current active interrupt priority

    Jonathan Weber
    Jonathan Weber

    Hi everybody,

    We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it to user tasks.

    In our implementation we need to determine…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to learn ARM

    Amey Chaware
    Amey Chaware

    Hi everyone!!

    I am looking to work on some projects using ARM. I have completed a basic course on ARM M3/M4 (UT Austin 6.01x by Jon Valvano and Ramesh Yerraballi) online. Now, I want to learn advanced things, especially real-time applications. How should…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Continue the Target using Serial Wire Debug Protocol

    harshan
    harshan

    Greetings,
                   sir, i am working on serial wire debug protocol and till now i succeeded in halt,write,erase,and reset the target. now i am trying to implement breakpoints and watch points on my custom debugger. for break point i read "the definitive…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How many times same interrupt can be in pending state at a time? (In ARM CM-3)

    sandeep tayal
    sandeep tayal

    Could not find the answer to How many times same interrupt can be in pending state at a time? (In ARM CM-3) e.g. :

    We are processing one interrupt INT_RX, at the same time 3 more packets received. so I expect 3 times more this interrupt to appear sequentially…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to acknowledge/clear active interrupt in Cortex-M4

    Deepak Jharodia
    Deepak Jharodia

    Hi all,

    I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to NVIC is de-asserted, the handler is called again. At…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M7 "zero overhead loop"

    Ari Mendes
    Ari Mendes

    Hi.

    In the page 22 of the document below informs that the cortex-m7 has "zero overhead loops" capability. I would like to know how it is done? Is there a special instruction for it?

    http://community.arm.com/servlet/JiveServlet/downloadBody/9595…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Return address from FIQ_Handler. Do we come back to the next instruction?

    Harshdeep
    Harshdeep

    Is it

    MOVS pc, r14

    or

    SUBS pc, r14, #4

    This is written in the ARMDEN0013D. but in the table it says next instruction whereas the SUBS pc, r14, #4 means the instruction which was interrupted.

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Which is best ARM starter board for 32 Bit 3D printer?

    Lindsey Scott Lewis
    Lindsey Scott Lewis

    Hello I was curious about which ARM launch/starter board would be best used to create an electronics controller for a 32 bit 3D FDM printer?  I was thinking that I've seen one project for the TI TM4C123G launchpad that might work.  But are there better…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • CPU Reset during a Debug session

    Kashif
    Kashif

    Hi All,

    I am trying to reset the CPU in the middle of a debugging session. I am using Application Interrupt and Reset control register by setting the SysResetReq bit in the SCB block. (this preserves the current debugging session also).

    However, as I am…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • STRD ATOMIC?

    loquat
    loquat

    Hi, I make a software for Cortex-A9 and Cortex-M4 (both uni-processor system).

    Question.

    Is 64bit-aligned STRD(64bit memory access) atomic ?

    (I know tha It is not atomic, but i don't know behavior.)

    For example:

    LDR R2,=buff

    mov R0, #1

    mov R1, #2

    STRD R0…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • [CM3]which clock sources can be closed?

    stupidMokey
    stupidMokey

    Hi bro,I am wondering which clock sources can be closed by software within stm32?thanks for helps.

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What's the difference between core, processor,cluster and CPU in ARM architecture?

    Grady
    Grady

    What's the difference between core, processor,cluster and CPU?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Fastest way to transpose array in cortex-m4?

    Josh Jordan
    Josh Jordan

    I've been seeing situations where I want to take a 32bit array of 32 elements and copy it so that all the bit 0s are copied into element 0, bit 1s copied into element 1, etc for all 32 elements.  This is always the processing bottleneck for applications…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to get Cortex m3 soft core

    Vivek Jayakrishnan
    Vivek Jayakrishnan

    Hi,

    I needed to know where i could get arm cortex m3 soft core. Its for my masters thesis for which i'll be also using Keil uvision 5.

    Thanks in advance

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 Unaligned access with STR single word access

    Saqib Ahmed
    Saqib Ahmed

    Hi there,

    I am getting a hard fault for accessing an unaligned memory address with STR single word access on a cortex M4 processor (Infineon XMC4500 F100k1024). Cortex M4 manual says that:

    Unaligned support is only available for load/store singles (LDR…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problem: WFI instruction slowing down SYStick interrupt

    Saqib Ahmed
    Saqib Ahmed

    I've configured my Infineon relax kit for max frequency(120 MHz). I've set my SYSTick for a periodic interrupt of 10 ms. For power saving, I use a WFI assembler instruction whenever my processor is idle. WFI (wait for interrupt) should put the processor…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What is the advantage of floating point of CM7 versus CM4

    Rastislav
    Rastislav

    Hi all,

    I did some of the investigation based on comparison of FPU based algorithms on CM4 and CM7 cores. All the code/data were placed into the single cycle memory with full utilization of modified / true Harvard architecture, it means:

    - on CM4 - code…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • ldm/stm with not aligned 4byte

    Paul
    Paul

    Hi experts!

    I want to use ldr/str or ldm/stm to copy memory not aligned 4bytes.

    I know their input address should be aligned by 4 bytes.

    but is there any solution to use ldr/str or ldm/stm though src or dst isn't aliged 4byte by modifing following code?…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • 1-cycle multiply, 64-bit result,  reciprocal?

    Sean Dunlevy
    Sean Dunlevy

    Can someone tell me how many extra gates the 1-cycle multiply uses? If there was a 64-bit result, how many more gates would be used? Can these gates also be used to find the reciprocal of a number so instead of divides, the coder multiplies the reciprocal…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Question is on WIC-CM4 interface

    Dhaval
    Dhaval

    Hi,

    Assume system configuration is: CM4 in a switchable power domain and WIC in always on domain. Also in response to "seeldeep" if the power management unit is powering down the CM4 and with no logic retention.

    Given this system configuration…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Replacing branch-instruction with address assignment to PC

    Raad
    Raad

    Hi,

    in a thumb-assembly file (my toolchain is gcc 4.8), I want to replace a branch with address assignment to the program-counter.
    So instead of:

    b   lbl

    I want to have something like:

    pc = address(lbl)


    This solution works. Here, I use the following code to…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
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