• Rowhammer bug on ARM

    Frederick
    Frederick

    Is there anyone who is working or having background knowledge on the rowhammer bug on ARM-based devices ?

    Thank you.

    • 13 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • OSv guest encountering EC - "Unknown Reason" sync exception (ESR = 0x2000000) on Raspberry PI 4B host with KVM on

    Waldek
    Waldek

    Hi,

    I am one of the OSv unikernel developers and I have been stuck trying to figure out the problem described here - github.com/.../1100 - for a long time now to no avail. And I am looking for any more suggestions on how to debug it further.

    In essence…

    • 14 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • Disable Cache L1 et L2 Armv8

    Rifakst
    Rifakst

    Hi

    I work with the ARMV8 architecture, I want to disactivate L1 cache ,

    to disable the L1 cache I found in the user manual
    "" The SCTLR.I bit enables or disables the L1 instruction cache. ""

    my question here is: I did not find in the…

    • Answered
    • 16 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to disable the branch prediction on armv8

    Rifakst
    Rifakst

    Hello,

    I am working with ARMV8 Cortex A72 architecture,
    i want to know can i turn off branch prediction?
    and how can i do it?

    best regards,

    • 20 days ago
    • Processors
    • Cortex-A / A-Profile forum
  • imx-atf boot flow

    segfault
    segfault

    Hi,

    imx-atf allows alternative boot flow by preloading a BL33 (custom) image into memory.

    Are there any instructions on how to use BL2 to boot an EL3 payload for pre-production test work ?  How to use EL3_PAYLOAD_BASE common build parameter ?

    Also, there…

    • 3 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Inconsistent shareability domain on tlbi instructions

    josecm
    josecm

    I'm using a IMX8QM system which features a dual-core A72 cluster plus a quad-core A53 cluster. Running on EL2 from one of the A53 cores I want to unmap a single page for all cores, so after I remove the entry for the page table I use the tlb invalidation…

    • Answered
    • 3 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • DRAM address mapping on a Cortex-A72 ARMv8

    Frederick
    Frederick

    HI Everyone,

    I need help about DRAM address mapping on a Cortex A-72 especially my question is : given two physical memory addresses how can i know if they are in the same DIMM, Rank and Bank ?
    is there any bit to check for it ?

    Thank you.

    • 4 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Time measurements ARM v8 platform running Linux

    Frederick
    Frederick

    HI Everyone,

    This is my first time here.

    I need help about time measurements on a Cortex-A72 (Arm v8) 64-bit.

    I have been trying to read the cycle counter (i have got root privileges on machine), but i can't.

    my c code:

    #define _GNU_SOURCE
    #include…

    • 4 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • -

    Hamed
    Hamed

    -

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM A64 Page table

    venmer
    venmer

    Hi,

    I have a question on ARM page table.

    I am running a bare metal application on Cortex A72 and i have a failure with my application.

    Upon debugging the failure, i found an address which is contributing the failure. our Bare metal application is responsible…

    • 11 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Atomic write (LDAXR/STLXR) causes infinite loop on Cortex-A72

    zhak
    zhak
    I have code which runs on Cortex-A72 (AArch64) and it disassembles to the following:
     0:   d53800a9    mrs x9, mpidr_el1
     4:   92400529    and x9, x9, #0x3
     8:   b4000069    cbz x9, 0x14
     c:   d503205f    wfe
    10:   17ffffff    b   0xc
    14:   10ffff69…
    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to generate delay in CPU?

    MNB
    MNB

    Hello,

    I am trying to generate delay in CPU. For instance after writing a register, I want to read it again after 1000ns. What should be the C code or the assembly code for the same?

    Thank you

    Nishank Bansal

    • Answered
    • over 1 year ago
    • Processors
    • Classic processors forum
  • A72 not handling IRQ properly

    MNB
    MNB

    I want a register write to happen whenever there is an interrupt at irq pin of core 0 and I have written the code for the same. A72 branches to address 0x18 (V=0 and VE=0) by default whenever there is an irq interrupt. On this instruction address, instruction…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to determine which core is generating the AXI read transaction in a multi core processor?

    MNB
    MNB

    I am currently working on Cortex A72 processor. I have generated hex file by compiling the c code file and asm file using Tizen compiler. The code consists of boot code for each core and each core starts executing its own code as soon as reset is deasserted…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trustzone and Hardware virtualization support

    Justin
    Justin

    Hello,

    I am looking for a development board that has an open Trustzone and hardware virtualization support. Do the Juno boards support this?

    Looking around the ARM A72/57/53 chips all support Arm Trustzone and have hardware virtualization support, however…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Performance effect because of removing some instructions from ARMv8?

    Natesh Raina
    Natesh Raina

    I was going through the ARMv8 Architecture Reference Manual and I came to know that it does not support many instructions that were previously supported by ARMv7 architecture. For example ARMv8 does not support conditional codes and have a seperate instruction…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • which processors are very advanced processors

    karthi
    karthi

    i just want to know which processors are very advanced processors in  cortex-A,R and M series.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • CA72 transactions IDs

    Jay Zhao
    Jay Zhao

    In the TRM of CA53, I see some descriptions of the encodings for AWIDM and ARIDM, and it's quite clear to distinguish Read & Write transactions from different cores.

    But in CA72, I can't find such descriptions.

    In my simulation, tt seems that…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • OPS/core/cycle on A72

    fset89
    fset89

    I want to perform profiling on my neural network and I need to know the OPS/core/cycle of the A72 processor. Where can I find this information?

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Feature Comparison ARM v8 series

    techguyz
    techguyz

    Hi Experts,

    Please specify is there any document on the Cortex A series comparison sheet for the various properties.

    For example, Table 2.1 in the https://static.docs.arm.com/den0024/a/DEN0024A_v8_architecture_PG.pdf has details on A53 and A57. Likewise…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Sampling/tracing memory addresses

    chansen3
    chansen3

    Is there any ARM tool that will sample or trace addresses of memory accesses for a processes?  And specifically for a Cortex A72-A.  It appears that there is support for this with the Statistical Profiling Extension or an Embedded Trace Macrocell, but the…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Deploy State-of-the-Art Deep Learning on Edge Devices in Minutes

    Amir Alush
    Amir Alush

    Deploying advanced deep learning algorithms on edge devices – especially for computer vision applications like autonomous vehicles and IoT – requires special capabilities. At Brodmann17, our mission is to create practical, neural-network based…

    • over 2 years ago
    • Processors
    • Processors blog
  • about cortex-A72

    Kallooran
    Kallooran

    hello guys, can you tell me the number of execution units in Cortex-A72 and the number of clock cycles it takes per instruction?

    Thanks in advance

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Security, the Fundamental Element in Next-Generation Networks

    Jim Wallace
    Jim Wallace

    Authors: Jim Wallace, Arm; Joseph Byrne, NXP

    It’s hard to imagine a day without relying on a computer or smartphone at work, when shopping or banking, chatting with friends, or even listening to music or watching a show. At the same time, it’s hard not…

    • over 2 years ago
    • Processors
    • Processors blog
  • Arm partnership providing the foundation for next generation networks

    Jim Wallace
    Jim Wallace

    Authors: Jim Wallace, Arm; Joseph Byrne, NXP

    Service providers or anyone involved in building out next-generation networks are faced with complex challenges today as they seek to evolve, future-proof, and secure their networks to meet the ever-increasing…

    • over 2 years ago
    • Processors
    • Processors blog
  • View related content from anywhere
  • More
  • Cancel
>