Hi All.

Does ARMv8-A has something similar to VC_CORERESET bit in Debug Exception and Monitor Control Register of ARMv8-M ; which enables halt on reset vector on warm reset?
Or is there any other method to halt the ARMv8-A core in reset vector?

hi.

I have a question about floating point performance relative with fpsr register.

When i initialize hardware, there is floating point exception(inexactly floating-point exception).

I did not set fpcr.IXE=0, so fpsr.IXC is set. not occur exception.

Hi,

I'm searching for the documentation for the exception classes in ESR_ELx. But currently couldn't found any information.

Want to port my bare-metal applications to AArch64. I own a PINE64 Rock64 (quad core Cortex-A53) board, which I want

Hi

I study coresight test with cortex A53 CPU.

I get FIQ interrupt when I running helloworld test in ini_libc function. But I don't known why.

I use gcc-linaro 4.9 toolchain : aarch64-none-elf-gcc  with glibc 2.14

Set CPU config pin aa64naa32 to 1…

There is a reference to erratum 820719 in the NXP S32V Errata list but I can't seem to find any reference to this erratum anywhere in ARM documentation. Is this erratum still valid?

Excerpt from S32V Errata document (refer: https://www.nxp.com/docs…

Hi,

I am using IDE Xilinx SDK 2019.1 for my application and running it on ARM cortex a53  processor with Neon and floating point engine support available. I am working on a bare metal application.

The problem I am facing is that, I am unable to understand…

I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.

I tried -mfpu…

I am using ARMv8 GCC compiler and I would like to optimize Neon Intrinsics code for better execution time performance. I have already tried loop unrolling and I am using look up table for the computation of log10. Any ideas?

Here is the code:

static inline…

Hello,

we have a board using Armada 3720 SOC, which contains two Cortex-A53s and one Cortex-M3 used as secure-coprocessor. The interrupt controller is GIC-500.

The M3 has access to all registers that A53 can see. The first A53 has RVBAR at 0xffff0000 where…

Dear Experts

I am working on a target that contains quad A53 cores operating at 1GHz. The operating system idle loop contains WFI inline assembly instruction. I know that the Core Clock halts during the WFI instruction which can be seen on the PM_CCNTR…

In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code:

AArch32 
Px 
        PLDW[R1]                     ; preload into cache in unique state 
Loop 
        LDAEX R5, [R1]               ; read…

 Dear All,

I am using a raspberry pi B+ that uses a Broadcom BCM2837 SoC with an ARMV8  processor. I want to get the cpu temperature in a Linux kernel file. Like in x86, I can use rdmsr_on_cpu function to load the temperature from MSR_IA32_THERM_STATUS register…