• Different performance in HYP and SVC mode ARMv7A?

    ivanpavic
    ivanpavic

    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Non-Cacheable memory and DMA on armv7a

    Vincent Siles
    Vincent Siles

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACP and DMA usage on A53

    leslielg
    leslielg

    Hi,

    I'm using DMA transfering data through ACP on A53. 

    According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?

    Then software must re-configure DMA then re…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • A53 preload mechanism

    MarkL
    MarkL

    Hi,

    I am reading the A53 MP Core doc.

    My question is related to instruction preloading in aarch64.

    In case of a very large block of code with no function calls, I want to make sure the L1 cache is always filled.

    Question 1:  Will the PLI instruction first…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MRS [A/C]PSR latency armv8-a?

    MarkL
    MarkL

    HI,

    Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?

    I want to read the flags with no jump (and it is critical).

    Thanks

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Data synchronization Barrier and cache.

    Marcin.Kondraciuk@secom.com.pl
    Marcin.Kondraciuk@secom.com.pl

    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before starting copy by DMA, I clean data cache by MVA…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A15 vs A73 speed Odroid XU4(A15 1,8GHz) vs Hikey 960(A73 2,4GHz)

    MICHAL LAZO
    MICHAL LAZO

    I did some benchmark Odroid XU4(A15 1,8GHz) vs Hikey 960(A73 2,4GHz) 
    discuss.96boards.org/.../2140
    And I would expect better results
    but it looks like it is pretty much same if we have A15 on same frequency

    Anybody can explain this?

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is there any tool to profile power of a C code on Linux running on Cortex A53?

    B Ravikumar
    B Ravikumar

    We want to profile the power consumed by an application running over Linux kernel 4.2.x on Cortex A53. Is there any tool which can help here?

    regards,
    Ravi

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Programming TZASC in Secure Mode

    sarjoon
    sarjoon

    Hi everyone,

    I am working to setup the TZASC on I.MX6UL based dev platform platform.

    I did the following.

    - Running SPL bootloader from OCRAM

    - Disable the bypass (by setting GPR9's bit 0 to 1 on my boards).

    - Setup 2 regions

           * Region 0 - Base…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • CP15SDISABLE

    AALLeeXX
    AALLeeXX

    Hello,

    it maybe not the right place to ask, but friends on PI forums seem not aware either so, i ask here in case;)

    The question is simply, where is this input mapped on the raspberry PI2 ? Is it a conventional input ? Is it really mapped or implemented…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • is there any simulator for ARM CORTEX A series

    dhrumil Shah
    dhrumil Shah

    I was working on smart wearable using ARM Cortex A series so there is any other simulator for ARM CORTEX A

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to execute 32-bit ARM assembly in a 64-bit environment

    sandrosart
    sandrosart

    Hi everyone,

    I have a 32-bit arm assembly program and I'd like to run it in a 64-bit os (in particular, in a raspberry pi 3 board). Which libraries do I need in order to do that?

    Thanks in advance.

    Sandro

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory read error at 0xF8000008: Cannot read write-only register.

    doner_t
    doner_t

    Hello, 

    I am not sure, here is correct place to ask this question. But I want to try ; 

    I have received an error :  Memory read error at 0xF8000008: Cannot read write-only register, When I try to debug a basic memory test code, in CortexA9.  I can not even…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    thomas_cp
    thomas_cp

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A53 : Cache policy setting

    PrabhuKrishnan
    PrabhuKrishnan

    Hi,

    Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? 

    I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • [A53] Hex file is Huge when generated fromo ELF

    AshishK
    AshishK

    Hi , 

    If I generate the elf file from the Default bootcode and pagetables , I get a very small size but 

    after mapping the Stack pointer to SRAM , I am getting a huge HEX file. 

    Here is the  loader file  code 

    ============================================…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trying to find basic performance measurements of ARM cores

    eskimoalva
    eskimoalva

    Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.

    I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Launching bare-metal firmware at EL2 (Hyp) on QEMU with ARM Trusted Firmware?

    gcicero
    gcicero

    Hi experts,

    I am recently developing some bare-metal code for a Cortex-A57 Aarch64 on QEMU (Virt platform) for playing with the Virtualization Extension. I first used one core and I developed a bootloader from scratch that switches the execution from…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • [Cortex-A53] STP instruction stores out of the specified memory

    Emmy0
    Emmy0

    Hi Experts,

         I have a question about "STP" instruction in Cortex-A53.

         STP W6, W6, [SP, #20]  --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted.

         I don't know why cause it. 

        Can you help to explain the reason…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SMC not going into EL3

    yaron alterman
    yaron alterman

    Hello experts,

    In my project I need to write some bare metal code in order to boot my software (A VxWorks image), and would like to make the absolute minimum configurations before loading the VxWorks image, which then does the major part of the configurations…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM cortext A53 Physical Address Flush

    m0sf3tz
    m0sf3tz

    Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then L2 assuming there is no L3 to get to system memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 - Enabling/Disabling the Caches

    M.Eladouly
    M.Eladouly

    Hello,

    I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).

    In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.

    What I need is to know…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Interrupt collector

    RCReddy
    RCReddy

    Hi All,

    I am using Arm Cortex-A53 based board.I modified a driver module and the interrupt processing.

    I have a fundamental question:

    Since Arm Cortex-A53 can handle 16 primary interrupts, what happens if all the interrupts arrive at same time. Though…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to know if a RAM is compatible with an architecture or a processor?

    wchgoldbach
    wchgoldbach

    I don't have much experience in building an embedded system from 0. I want to ask a general question as showed in the title through an example.

     

    I choose Cortex-A9 (ARMv7-Profile A architecture) as CPU.  Then I want to use DDR3 RAM of Alliance memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A53 backward compatible with AXI-4 interconnect

    Ed Leung
    Ed Leung

    Hi,

    The Cortex-A53 core supports either ACE or CHI as its master interface.  Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if Cortex-A53 ACE interface is connected to an AXI-4 interconnect…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
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