• Cortex-A8 - accessing banked registers from monitor mode

    Jitesh Shah
    Jitesh Shah
    Note: This was originally posted on 20th March 2012 at http://forums.arm.com

    Hi Group,
    I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of the SVC mode.

    I know two ways I can do it:

    1) Using the…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Sampling/tracing memory addresses

    chansen3
    chansen3

    Is there any ARM tool that will sample or trace addresses of memory accesses for a processes?  And specifically for a Cortex A72-A.  It appears that there is support for this with the Statistical Profiling Extension or an Embedded Trace Macrocell, but the…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to implement voice and audio processing on Arm with Alango Technologies

    Chris Shore
    Chris Shore

    Picture your smart assistant at home: you say a command, and it recognizes your voice, processes what you’re saying and responds. This is an example of a multi-sensor device that requires signal processing. Designers of compelling voice communication…

    • over 1 year ago
    • Processors
    • Processors blog
  • how to understand L1 cache but L2 & L3 non-cached

    phil9980
    phil9980

    A5.6.6 Memory Behavior
    The Cortex-A55 core supports all the ARMv8 memory types.
    However, the following behaviors are simplified and so for best performance their use is not recommended:
    Write-Through

    Memory that is marked as Write-Through cannot be cached…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Issue with WatchDog reset De-asserting

    BAB
    BAB

    Hi,

    I am working on ARM CortexA9 processor. I could able to enable both l4wd0 and l4wd1 watchdogs. Issue is system is resetting but not rerunning. I tried changing the register values of reset Manger as well.

    How to de-assert the reset and make the system…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Watchdog timer not entering ISR

    sherry
    sherry

    I am using ARM cortex A9 core in Zynq. I want to trap any bugs in hardware or my firmware. I intend to use watchdog module in interrupt mode and connect it to Global interrupt controller (ScuGic). When the watchdog counter decrements to zero, it is to…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • New Arm Cortex-A77 CPU continues path towards compute performance leadership

    Stefan Rosinger
    Stefan Rosinger

    Following the great success of last year’s Arm Cortex-A76 CPU, we are excited to launch the third generation DynamIQ ‘big’ core Arm Cortex-A77 CPU. It is the second in the family of high-performance, highly efficient CPU products built…

    • over 1 year ago
    • Processors
    • Processors blog
  • Binary Semaphore upset by FIQ

    LdB
    LdB
    semaphore_take:   

        mov    w2, #1                 // LOCK value
        dmb    sy                     // ensure all observers observe data before aquire is attempted
        ldaxr    w1, [x0]             // attempt to read and aquire lock
        cbnz    w1, semaphore_take    // lock is not zero so loop and try and aquire again
       
    …
    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A8: memcpy() into DMA buffer hangs on NEON instructions

    LeonP
    LeonP

    I am cyclically filling the mmap-ed DMA buffer with my data by copying it from "normal" memory in 290 bytes chunks.

    At the first cycle memcpy always passes OK. At the second cycle it hangs in __memcpy_neon routine (at least this is what the…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Technical Webinar: ML on Arm Cortex-A FAQ

    Jason Andrews
    Jason Andrews

    If you missed the recent technical webinar, Machine Learning on Arm Cortex-A –  it's now available on demand. This showed how developers can move neural network (NN) workloads around an SoC quickly and easily using Arm NN, facilitating software portability…

    • over 1 year ago
    • Processors
    • Processors blog
  • CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM

    chinatiger
    chinatiger


    hi, experts: 

    In Cortex-A57 TRM chapter 4.3.66 :

    It defines CPUACTLR_EL1 register, but this register name is not CPUACTLR_EL1.

    Its name is S3_1_C15_C2_0.

    Why?

    best wishes,

    hi

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to read PMU correctly for multi-thread on dual core Cortex-A9 under userspace

    yunwu
    yunwu

    Hi,

    I have enabled the userspace pmu access by building a kernel module for both core on Cortex-a9. Then I follow the standard procedure of pmu counting:

    1. Disable performance counters

    2. Set cycle counter tick rate

    3. Reset performance counters

    4. Enable…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM: 743626—An imprecise external abort, received while the  processor enters WFI, may cause a processor deadlock

    Manyam
    Manyam

    Can someone explain more about this issue, and please provide the fix for this issue.

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does ARMv8 SOC support cache lockdown?

    chinatiger
    chinatiger

    hi, experts:

    In ARMv8 Arch reference manual, it said:

    ARMv8 supports cache lockdown feature, but it is implementation defined.

    So, my question is:

    Has the integrated L2 Cache controller some registers related lockdown feature settings?

    I didn't find them in…

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A8 Instruction Cycle Timing

    barney vardanyan
    barney vardanyan
    Note: This was originally posted on 17th March 2011 at http://forums.arm.com

    Hi) sorry for bad English

    I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
    but I have no idea how can do this work…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • VMSAv8-64 and spinlock

    Ciro Donnarumma
    Ciro Donnarumma

    Hi,

    I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

    I'm writing bare-metal code, without…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareable domain and cache policy problem

    zhi
    zhi

    Hi,

    I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • dump MMU translation table for A9 in Linux

    mivascu
    mivascu

    Hello,

         I would like to know how to read the translation table info for A9  from embedded Linux.

         In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux kernel.

         Should I just dump TTBR0/TTBR1 registers…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Explain 8 stage pipeline of ARM Cortex a7?

    rakeshgp3
    rakeshgp3

    Brief explanation of each stage of ARM pipe-lining.  

    How many Neon pipeline stages are their?

    What is dual issue in ARM pipe-lining?

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • MMU initialization for an ARM multicore system

    ddn
    ddn

    I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).

    On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • MMU and Cache configuration

    ZbinAhmed
    ZbinAhmed

    Hello there,

    I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.

    I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache

    Steps :

    1.Disable cache, branch predictors

    2. Invalidate…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot!

    sam0220
    sam0220

    when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot!

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • aarch64 Exception Level Sw itch from EL1 to EL0

    michaelyuanfeng
    michaelyuanfeng

    Hi Expert,

    I am working on a simple kernel and test it on Qemu which supports RasPi3. During the boot level. Ras Pi goes to EL3 level, and I set spsr_el3 to 1 and elr_el3 to kernel_main and then use eret to enter EL1 mode. My problem is I create a kernel…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A8 PLD

    cc90202
    cc90202

    Good morning, I'm studying ARM assembly, Cortex A series. Reading the ARM documentation I found out this paper (Cortex A8, fast memcpy examples). My attention went to the PDL instruction, preloading into cache. I have read about it on the ARM manuals…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Armv8 Memory Mapping

    AnthonyPaulO
    AnthonyPaulO

    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which I can determine the memory address being accessed…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
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