• reason for ARMv8 EDSCR err bit set

    Strong
    Strong

    Hi,

    I'm working on a project which is for debugging cortex-a53 through Jtag interface.

    The Jtag clock TCK is set to 300kHz which is pretty low, and I can properly read back debug registers such as EDSCR and EDPRSR. EDPRSR is 1 before I issue the 'halt…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    RadarSong
    RadarSong

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is there any available data about the PPA comparison b/w Cortex-A7 and Cortex-A53

    Shane Yu
    Shane Yu

    Performance (DMIPS/CoreMark/SpecInt, etc.), Power and Area comparison on an apple-to-apple basis? Thanks a lot!

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use the amba bus?

    Idan
    Idan

    Hello,

    i have the Zedboard which contains arm Cortex-A9 cortex with the amba bus..

    i have searched a lot but I probaly miss the point.

    i want to use data and to transfer  data from the processing system to the programable logic section via the amba bus…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Regarding mismatched memory attributes and cacheability

    Hemant
    Hemant

    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ

    My question is specific to the case when it is only the cacheability…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why the address width of MMU-500 is different with Cortex-A53/57?

    wangyong
    wangyong

    I find the description below from MMU-500 TRM.

    Address width

    The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address

    bus…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does ARM have a time counter mechanism?

    Cyberman Wu
    Cyberman Wu

    Say, like Time Stamp Counter of x86, or Time Base of PowerPC, which can used to

    do some performance profiling.

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Guidelines on reducing Cache Miss rate

    techguyz
    techguyz

    Hi Experts,

    Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ?

    If it is more specific to A/R/M then its great..

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Minimal Frequency of Operation

    techguyz
    techguyz

    Hello,

    Is there any data regarding the minimum and maximum frequency a processor can operate in ARM V-7 ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why A9 is multicore by A8 doesn't

    techguyz
    techguyz

    Hi Experts,

    Which factor in processor decides whether it can be used in multi-core or not ?

    Like as per my understanding A8 is used in single core whereas A9 is used in multi core. So which distinctive feature in A9 favors the multi core application ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACTLR[1] question in Cortex-A serias SOC

    chinatiger
    chinatiger

    hi, experts:

    I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.

    I have some questions about out cache concept in Cortex-A7.
    1. Some program disable outer cache by setting ACTLR[1] = 0.

       So, is it only available with Cortex-A9…

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Basic cortex A9 architecture question (memory area division)

    Senthil Kumar Rajagopal
    Senthil Kumar Rajagopal

    Hello all,

    I have a client who has the following requirement. He uses an Cortex A9 (dual core) based SoC chip .

    The system has two Flash ROMs - Flash ROM 0 and Flash ROM 1. Each of these flash roms has a boot loader and user program.

    On Reset, the CPU 0…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 initialization code & TrustZone/ Secure Boot

    Vincent Siles
    Vincent Siles

    Hi,

    I just got a raspberry pi 2 and I'd like to play with Trustzone.

    People on the Raspberry forum http://www.raspberrypi.org/forums/viewtopic.php?p=697474#p697474 explained me how to

    get my hand on the boot of the 4 core A7 CPU, and I managed to boot…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • bootloader writing

    harshan
    harshan

    greetings,

                  as i know the boot loader is the start-up for most of controllers today. till now i just used the boot loader written by someone but i don't have any idea about it how to write it  what are the things we have to include and what…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to do cache invalid on Cortex-A53?

    yan.wy
    yan.wy

    hi,

         I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.

         Could you give me any suggestion about cache invalid? Thanks!

         The program…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9 core registers

    Jay Zhao
    Jay Zhao

    In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems.

    So how can I match them with R0-R14, especially…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache Memory Requirement

    techguyz
    techguyz

    Hi Experts,

    How to derive the cache memory requirement for the working of the software ?

    I could understand that each of the A/M/R processors have its own applications and build with its own Cache size MPU/MMU configurations but how this is derived with…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which ARM processor is HSA compatible?

    Samy CHBINOU
    Samy CHBINOU

    Hi,

    I am new to the ARM community. I am currently studying the HSA (Heterogeneous System Architecture). ARM is member of this foundation.

    I wonder which processor from ARM is HSA enabled? And on which devkit (raspberry, ODROID, or other) So I can use it…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • On Chip RAM is slow after enabling MMU, and using external ram aborts

    Gopu
    Gopu

    Hello All,

           I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.

    Issue 1:

    But what I could notice is code region in external ram is executing faster than internal ram.

    If I disable…

    • Answered
    • 7838.zip
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Supported AXI transfers on Cortex-A9?

    Martin Trummer
    Martin Trummer

    Hi folks,

    The technical reference states that only a subset of possible AXI transactions are actually generated.

    This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html

    What happens for this table if the master…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can we run the Cortex-A53 cores at different clock speeds ?

    Ravinder
    Ravinder

    Dear ARM Group,

    Can we run the A53 cores at different clock speeds?

    if YES,  How does it effect the complete A53 (L2 cache etc) and system?

    if NO,  What are the constraints ?


    could you please give a detailed description on this?


    Thanks,

    Ravinder…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • updating CPSR in USER UNPRIVILEGED mode

    anoop
    anoop

    as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is user mode, since user mode is unpriviliged so i must…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How does128Byte WriteLineUnique transaction map to a cache with 64Byte cache line size?

    Hanan
    Hanan

    Hello,

    I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to set endianness in ARM Cortex-A8

    ranjithkumar ds
    ranjithkumar ds

    Hi,actually i need to run big endian code but i don't know how to set endian option in cp15 registers could any suggest me how to set EE bit set

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • share memory between core0 (linux) and core1 (bare-metal)

    Mike
    Mike

    Hello,

    i want to use the arm cortex a9 to share memory between both cores. are there any examples online?

    Thanks,

    Mike

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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