2020 has been a big year for the Windows on Arm (WoA) ecosystem. The new ‘third generation’ of devices reached the market, including the world’s first ever 5G laptop – the Lenovo Yoga 5G – and Samsung Galaxy Book S. However, it is not just…
2020 has been a big year for the Windows on Arm (WoA) ecosystem. The new ‘third generation’ of devices reached the market, including the world’s first ever 5G laptop – the Lenovo Yoga 5G – and Samsung Galaxy Book S. However, it is not just…
Back in May 2020, we launched our latest mobile solution offering including the Arm Cortex-A78 CPU, Arm Mali-G78 GPU and Arm Ethos-N78 NPU. At the same time, we also announced the Cortex-X Custom (CXC) program, which allows for customization and differentiation…
Hi, I am looking at ARM CMSIS code for biquad float32 implementation. This is written for Cortex-M as documentation states. How much effort would be needed to port this code to Cortex-A53? The code should be fast, optimized using intrinsics, not assembly…
At the heart of everything, we do at Arm is the need to deliver performance with efficiency. We need the performance improvements to enable and improve the range of digital immersion use-cases on mobile devices. These cover common productivity, communication…
In late 2018, we talked about the benefits of the second generation of Windows on Arm laptops, which use the Snapdragon 850 SoC built on Arm Cortex technology. An Arm-commissioned benchmarking paper showed how these 2-in-1 laptops were ahead of the competition…
Hi experts,
I do an experiment about cpu power with a board which has 4 cores of Cortex-A55.
I try to power on/power off core1~3 parallelly.
Sometimes Both PACCEPT and PDENY are zero after changes the power state.
If I only power on/power off one core,…
During the past 25 years the mobile form factor has evolved into many different designs. In the 90s, there were the ‘brick’ style GSM powered mobile phones, which gradually evolved into the popular ‘candy-bar’ designs of the early 00s. As we moved into…
Hey everyone,
I am working on STM32MP157-DK1 with trustzone cortex-A.
I want to use the SPI in secure side, but it's possible only with SPI 6 that is not mapped to the outside.
It's possible to activate SPI (1 ... 5) peripherals in secure side ? if…
Hello,
I have run two different bare-metal programs on two corresponding ARM cores in Cyclone V (Cortex-A9) in DS5 using JTAG line. The SDRAM is shared between the two cores as is evident from the cache settings which is set to "shared" by default. Core…
Hello,
I am using a quad-core Cortex-A7 (on Raspberry PI 2). I run a Linux on Core 0,1,2 and a baremetal application on Core 3. My goal is to protect the baremetal application from the rest (i.e., the linux side). Initially I thought that I can do this…
how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm form?
if there are some documents which describes it in detail?
In Chinese:
我目前用cortex-A8(armV7)来开发项目,由于一些算法需要在ARM端跑,算法需要优化,需要写arm汇编指令,
想知道,armv7每个指令执行消耗的周期…
Hi,
I am just trying to learn the linux kernel booting process for arm32 Cortex A9 multi core SOC. I had understood the concept of booting in linux, but I am confused about the section where secondary cores enabling from primary core. Can somebody briefly…
I am examining ARM Cortex-A8 program flow prediction abilities, in document of Cortex-A8 arm specified that it would predict LDM instruction with PC in register list. now i have a question, if we have some condition in the instruction, such as "LDMGE…
I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code:
char SecretDispatcher[256 * 512];
int counter = 0;
//evicting SecretDispatcher from cache
...
while(counter < (512 * 9 + 1))
{
//evict…At Arm we’re often asked by partners, developers and other interested parties within the complex and huge machine learning (ML) ecosystem which processors are best at performing specific ML actions on different devices. As described in this Arm…
In AHB-Lite cases, every transfer starts with address phase with signals from master.
And also in multi-master cases, arbiter decides with whether it can GRANT bus access to other masters or not.
So, I think it's fine to only let masters or arbiters to…
Hello,
I'm reading ARMv7 architecture reference manual and there are the following keywords:
It looks like that outer/inner cacheable means that a region of memory can be cached in L1…
Hi everyone! Please help me.. i have a project with a custom axi slave design that implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example slave and read the data back. The problem is…
I have a question related to data fetch, when on gdb debugger I do an address read say as:
X 0x81000000
Then it will fetch 64 bits as you told in reference to Cortex A9
If further I do
X 0x81000004
Will it fetch 64 bits again from 0x81000000 or it will use…
Hello Everyone,
I am new to ARM processors. I am trying to get a good handle on the low levels aspects of the ARM processor like exception handling. From searching the ARM website and looking at the data abort handler documentation I am pointed to this…
Hi All,
What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm? I know that they say it is compatible with ARMv7/8 ISA.
Regards
Nitin