• Questions about Generic Timer in ARMv8

    wangchj
    wangchj

    When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

    But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

    And, if…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • clean and invalidate cache behavior before same address read

    loquat
    loquat

    I am running on cortex-A17.

    when following,

    step1: STR  R0, [R1]       ; [R1] is cacheable

    step2: DCCIMVAC          ; clean and invalidate cache

    step3: LDR  R0, [R1]       ; memory…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Regarding ADFSR and AIFSR in ARM Cortex-A9 MPcore

    Niranjan Dighe
    Niranjan Dighe

    Hello all,

    I was debugging an imprecise external abort in one of our product based on i.MX6q and came across a register - Auxiliary Data Fault Status Register

    readable and writable by the following instructions -

    MRC p15,0,<Rt>,c5,c1,0

    MRC p15,0,<Rt…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to set secondary core's registers from primary arm?

    serhat
    serhat

    Hi all,

    Im working on Keystone II Tci6638k2k(4arm+8dsp) custom design board with u-boot. I understand that how u-boot working.

    U-boot gives entry point to other cores. Other cores take program counters with this way. But i want to give core registers too…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM cortex A15 hardware simulatenous multihreading.

    Mazen Ezzeddine
    Mazen Ezzeddine

    Dear All,

    Does ARM cortex A-15 support some kind of Hardware multithreading? how can I disable it?

    Thank you so much.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Coprocessor instruction differencies?

    Juha Aaltonen
    Juha Aaltonen

    Are there differences between coprocessor instructions and instruction2:s?

    I mean:

    MCRR vs. MCRR2

    MRRC vs. MRRC2

    MCR vs. MCR2

    MRC vs. MRC2

    LDC vs. LDC2

    STC vs STC2

    I didn't find any differences in the encoding except the condition code, and no differences in…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • NEON: Cortex A7 is 4 times slower than Cortex A8 ?

    Laurent
    Laurent

    I'm seeing Cortex-A7 cycle-timing table here :

    http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/


    For example, 

    VADD.F32 Dd, Dn, Dm takes 2 cycles

    VADD.F32 Qd, Qn, Qm takes 4 cycles

    same goes for VMUL..

    Is this really the case…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Register 'names' in instruction descriptions

    Juha Aaltonen
    Juha Aaltonen

    The registers in the instructions are usually 'named' Rn, Rm, Rd, ...

    Is there some deeper meaning in the names?

    Usually Rd seems to mean 'destination register'

    Sometimes Rn is the only operand, sometimes it's Rm. Also the place in the instruction…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • UNPREDICTABLE in instruction description (Lord! yet another question)

    Juha Aaltonen
    Juha Aaltonen

    In quite many instruction descriptions it says:

    if d == 15 then UNPREDICTABLE;

    What does this mean?

    Can the instruction really work in some unexpected way in each such case or what?

    I guess if I use a bit-reversing instruction on PC I should expect that…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Pseudocode for saturation (Oh no, not again)

    Juha Aaltonen
    Juha Aaltonen

    In some instruction descriptions there are calls to SignedSatQ (directly or indirectly).

    The pseudocode for SignedSatQ:

    (bits(N), boolean) SignedSatQ(integer i, integer N)

    if i > 2^(N-1) - 1 then

    result = 2^(N-1) - 1; saturated = TRUE;

    elsif i < -(2…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to measure program execution time in ARM Cortex-A53 processor?

    Rajeev Verma
    Rajeev Verma

    Hi,

    I was using following method to read clock in cortex-a15:

           static void readticks(unsigned int *result)

            {

                struct timeval t;…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Software Radio Based on ZedBoard and AD-FMCOMMS1-EBZ

    hgli
    hgli

    ARM friends,

    I have done some research on software radio based on ZedBoard and AD-FMCOMMS1-EBZ.

    ZedBoard is a development board which uses Xilinx Soc FPGA.

    Xilinx Soc FPGA includes ARM Cortex A9 dual-core and Xilinx FPGA.

    ZedBoard runs Ubuntu Linux operating…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SMMU initialization

    Dav
    Dav

    Hi,

    Where i can find step-by-step instruction how to init SMMU PA->IPA translation? (With procedure description)

    (i checked ARM ® System Memory Management document, but i was not found exact instruction how to setup correct translation).

    I have ARM…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ASR #32

    Juha Aaltonen
    Juha Aaltonen

    In the SSAT instruction description it says:

    ASR #32 Arithmetic right shift by 32 bits, permitted only for encoding A1.

    Encoded as sh = 1, immsh = 0b00000.

    What does that mean?

    Isn't ASR #32 the same as ASR #31?

    I understand that it shifts (with "sign…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The madman strikes again - ADD/SUB SP

    Juha Aaltonen
    Juha Aaltonen

    Is there something special in the instructions ADD (SP plus register, ARM) and SUB (SP minus register)?

    I didn't find anything different from the basic ADD  (register) and SUB (register) except the documentation:

    <Rd> The destination register…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • If non-secure world pass to virtual address (allocated by malloc or mmap) and ttbr value, how to find valid physical address in secure-world

    박주병
    박주병

    First sorry my english writing level. :-)

    In non-secure world using android system(linux kernel).

    I use big.little core Cortex-A53, Cortex-A57

    I was tested to 2case.

    previous stage.

         1. Linux allocation memory using(malloc or mmap)

    …
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is First-level table skippable? (VMSA)

    Jongseok Kim
    Jongseok Kim

    Hi forks. I am a newbie engineer for arm-processor and I have a question about VMSAv7-32.

    According to ARMv8 architecture manual, page 3592: arm processor can skip first level table if a first level table would contain only one entry..

    How arm processor…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How can we boot linux kernel in ARM FVP w/ TrustZone?

    Yoshiharu Imamoto
    Yoshiharu Imamoto

    Hello, everyone.

    Let me post a question regarding booting Linux on ARM FVP (with Cortex-A9 MPCore).

    I'm setting up an experiment which uses TrustZone on ARM FVP. I'm not sure which

    kernel to run in the secure world, but am sure to run Linux in Normal…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

    Kay
    Kay

    Hi Experts,

    I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.

    While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.

    When I run world shared memory test on a single core (using affinity), it works…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Funny asymmetry with banked register names

    Juha Aaltonen
    Juha Aaltonen

    Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but

    one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.

    In document (ARMv7-A/R ARM Issue…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • LDRT and rrx'd operand

    Juha Aaltonen
    Juha Aaltonen

    I was wondering about LDRT when the operand is rrx'd. Which where does the carry-bit come from?

    LDRT{<c>}{<q>} <Rt>, [<Rn>], +/-<Rm> {, <shift>}

    RRX Rotate right one bit, with extend. Bit[0] is written to shifter_carry_out…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Question about accumulator word length in A8 core

    Robert
    Robert

    Hi,

    I have used some 32-bit microprocessor cores (non-ARM), which has a long word-length accumulator for some DSP operations, to avoid over-flow etc. After I check A8 core document, it is a surprise that I do not see any about this specification. It looks…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to learn ARM

    Amey Chaware
    Amey Chaware

    Hi everyone!!

    I am looking to work on some projects using ARM. I have completed a basic course on ARM M3/M4 (UT Austin 6.01x by Jon Valvano and Ramesh Yerraballi) online. Now, I want to learn advanced things, especially real-time applications. How should…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to enable Neon in cortex A8?

    Rakshith Rao
    Rakshith Rao

    Hi,

          I am using beaglebone which has the processor TI Sitara AM335X. I want to make use of Neon coprcessor for my project, To enable neon, I have to follow these commands. But I can't access these registers ( especially FPEXC…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The reason why the exception frame forms on PSP?

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,


    I would like to ask the reason why the exception frame forms on PSP in the Cortex-M architecture.
    My understanding is that MSP (Main Stack Pointer) is the interrupt stack pointer and PSP (Porcess Stack Pointer) is the normal (user) stack…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
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