• Arm Cortex-A8 program flow prediction

    alireza11048
    alireza11048

    I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code:

    char SecretDispatcher[256 * 512];
    int counter = 0;
    
    //evicting SecretDispatcher from cache
    ...
    
    while(counter < (512 * 9 + 1))
    {
        //evict…

    • Answered
    • over 1 year ago
    • Processors
    • Classic processors forum
  • Kernel page table makes page fault although other core already mapped.

    Yeo Reum Yun
    Yeo Reum Yun

    Hi, expert. I'm making CacheFlush function by Virtual Address.

    I'm using TTBR0 for user area, and TTBR1 for Kernel Area, and I'm using Dual core, Cortex-A9

    I'm using Cache Flush Policy as Write Through about Kernel PageTable (Below KPT) itself…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Using the whole Cortex-A L2 Cache without external memory

    Laurent
    Laurent

    I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory.

    The CPU boots from an external 4MBytes SPI NOR FLASH chip.

    It has 512 KBytes of L2 cache and 32 KBytes…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to configure L2 cache in Cortex-A7

    Cherma Rajan
    Cherma Rajan

    Hi all,

    I am working on OrangePi board. The board configuration is,

    • Quad-Core ARM Cortex-A7, 1.6 GHz
    • 32 KB L1 I-Cache and 32 KB L1 D-Cache per core
    • 512 KB L2-Cache

    I have few queries related to Cache memory,

    1. How to disable L2 cache of Cortex-A7 in…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • CortexA8 L2 data loss

    Andreas Hauser
    Andreas Hauser

    Hi at all!

    I'm working with TI DM3730 (CortexA8 inside) and an external mobile DDR-SDRAM.

    The startup initialize MMU, L1 Cache and L2 Cache and Flow Prediction.

    Tests with about 256MiB of data show some data loss when L2 Cache is enabled.

    If L2 is disabled…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Need to invalidate L1 cache after DMA on Cortex A9

    Rohan
    Rohan

    Hi,

    I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The base code which Renesas supplies sets the caches…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9?

    Alex W
    Alex W

    I've been digging through the Technical Reference Manual (TRM) for the Cortex-A9 and so far it seems that it's possible to gather data about events such as hit and miss rates, but there doesn't seem to be anything on reading the raw data and tag bits…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache?

    Alex W
    Alex W

    The TRM for the Cortex-A53 has a section on direct access to various internal memories, including the L1 I-cache and D-caches. I'm successfully able to dump both tag and data for the I-cache and D-cache, but I'm having trouble making sense of the I-cache…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000

    Abhilash VR
    Abhilash VR

    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG.

    From JTAG, Read works properly but writes makes the specific cache line corrupted,

    Step 1 : Initial Setup

         1. Wrote an application Which runs from…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • PL310 cache synchronization

    Vincent Siles
    Vincent Siles

    Hi !

    I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation.

    - when I want to perform a synchronization, should I just wait for bit 0 (bit C) of the Cache Synchro register to be 0

    …
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A9 single core

    Vincent Siles
    Vincent Siles

    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:

    SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated

    as Non-Cacheable:

    • all pages marked as Write…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    RadarSong
    RadarSong

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Regarding mismatched memory attributes and cacheability

    Hemant
    Hemant

    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ

    My question is specific to the case when it is only the cacheability…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Guidelines on reducing Cache Miss rate

    techguyz
    techguyz

    Hi Experts,

    Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ?

    If it is more specific to A/R/M then its great..

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACTLR[1] question in Cortex-A serias SOC

    chinatiger
    chinatiger

    hi, experts:

    I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.

    I have some questions about out cache concept in Cortex-A7.
    1. Some program disable outer cache by setting ACTLR[1] = 0.

       So, is it only available with Cortex-A9…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to do cache invalid on Cortex-A53?

    yan.wy
    yan.wy

    hi,

         I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.

         Could you give me any suggestion about cache invalid? Thanks!

         The program…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache Memory Requirement

    techguyz
    techguyz

    Hi Experts,

    How to derive the cache memory requirement for the working of the software ?

    I could understand that each of the A/M/R processors have its own applications and build with its own Cache size MPU/MMU configurations but how this is derived with…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • On Chip RAM is slow after enabling MMU, and using external ram aborts

    Gopu
    Gopu

    Hello All,

           I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.

    Issue 1:

    But what I could notice is code region in external ram is executing faster than internal ram.

    If I disable…

    • Answered
    • 7838.zip
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can we run the Cortex-A53 cores at different clock speeds ?

    Ravinder
    Ravinder

    Dear ARM Group,

    Can we run the A53 cores at different clock speeds?

    if YES,  How does it effect the complete A53 (L2 cache etc) and system?

    if NO,  What are the constraints ?


    could you please give a detailed description on this?


    Thanks,

    Ravinder…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The merit of data cache cleaning

    Henry Choi
    Henry Choi

    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right?

    Kun.Niu
    Kun.Niu

    When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right?

    In the above question, the related region refers to the region seted to be cachealbe.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What's the single cycle Load-Use in ALU mean?(In Cortex-A7)

    Kun.Niu
    Kun.Niu

    What's the single cycle Load-Use in ALU mean?

    This is in the follow picture:

    CA7_detailpipeline.jpg
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How does the BTIC(branch target instruction cache) works?

    Kun.Niu
    Kun.Niu

    in cortex-A series, most core has the BITC(branch target instruction cache). It is contained in the prefetch unit.

    Branch Target Instruction Cache

    The PFU also contains a four-entry deep Branch Target Instruction Cache

    (BTIC). Each entry stores up to two…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How should I do if I want to enable only one single CPU on a Cortex A9 MPCore(2 CPUs)

    onion
    onion

    Hi, all

    When I was porting Minix 3 OS to Zedboard (Zynq 7000 All Programmable SoC) the system always hanged

    at refresh_tlb. What's strange is that refresh_tlb had been performed at KERNEL booting up, but when a user

    space process VM (for Virtual Memory…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Reordering between multiple loads

    Hemant
    Hemant

    Hello,

    I have a question if following sequence of instructions involving post-indexed LDRs could be re-ordered on say Cortex A8:

    To simplify, lets consider, r0 = 0xC, Cache line size 16 Bytes

    ldr     r1, [r0], #4     /* 1 */…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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