• The merit of data cache cleaning

    Henry Choi
    Henry Choi

    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    Kun.Niu
    Kun.Niu

    AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right?

    Kun.Niu
    Kun.Niu

    When the data CPU wants to access is not in the cache the related block will always be copy to the cache, is this right?

    In the above question, the related region refers to the region seted to be cachealbe.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What's the single cycle Load-Use in ALU mean?(In Cortex-A7)

    Kun.Niu
    Kun.Niu

    What's the single cycle Load-Use in ALU mean?

    This is in the follow picture:

    CA7_detailpipeline.jpg
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How does the BTIC(branch target instruction cache) works?

    Kun.Niu
    Kun.Niu

    in cortex-A series, most core has the BITC(branch target instruction cache). It is contained in the prefetch unit.

    Branch Target Instruction Cache

    The PFU also contains a four-entry deep Branch Target Instruction Cache

    (BTIC). Each entry stores up to two…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How should I do if I want to enable only one single CPU on a Cortex A9 MPCore(2 CPUs)

    onion
    onion

    Hi, all

    When I was porting Minix 3 OS to Zedboard (Zynq 7000 All Programmable SoC) the system always hanged

    at refresh_tlb. What's strange is that refresh_tlb had been performed at KERNEL booting up, but when a user

    space process VM (for Virtual Memory…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Reordering between multiple loads

    Hemant
    Hemant

    Hello,

    I have a question if following sequence of instructions involving post-indexed LDRs could be re-ordered on say Cortex A8:

    To simplify, lets consider, r0 = 0xC, Cache line size 16 Bytes

    ldr     r1, [r0], #4     /* 1 */…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

    Kay
    Kay

    Hi Experts,

    I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.

    While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.

    When I run world shared memory test on a single core (using affinity), it works…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Feature wise comparision for Cortex A series processors

    techguyz
    techguyz

    Hi Experts,

    Is there any document on feature wise comparison chart on the Cortex A series of processors ?

    Like,

    Cache for Cortex A8/9/52...

    MMU for cortex A8/9/52..

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache maintanance operation to PoC

    Luke
    Luke

    Hi experts,

    I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller).

    I'm refererring to the following operations:

    - DCIMVAC, invalidate data cache by MVA to POC      (mcr  p15, 0, r0, c7, c6, 1)…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Non aligned access in arm v7 going into exception

    Ramampreet Kaur
    Ramampreet Kaur

    typedef struct __attribute__((__packed__))

    {

    uint8_t    op_code;

    uint8_t    flags;

    uint32_t   logical_block_addr;

    uint8_t    group_num;

    uint16_t   tx_length;

    uint8_t    control;…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • System Error Interrupts in ARM V8

    techguyz
    techguyz

    Hi Experts,

    What is the use case of the system error interrupts in ARM V8 and when it will be invoked ? Does it common to all the guest OS running in EL1 ?

    Is it the physical input pin change like IRQs or instruction execution like WFE ?

    Regards,

    Techguy…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to understand L1 cache but L2 & L3 non-cached

    phil9980
    phil9980

    A5.6.6 Memory Behavior
    The Cortex-A55 core supports all the ARMv8 memory types.
    However, the following behaviors are simplified and so for best performance their use is not recommended:
    Write-Through

    Memory that is marked as Write-Through cannot be cached…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Getting processor and cache details

    karthikeyan.d
    karthikeyan.d

    I work on software that needs to know the processor and cache details. On x86 systems it uses the CPUID instruction to know about the processor family/model (Skylake, Icelake etc) and cache details (total size, line size, associativity etc). I am trying…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareable domain and cache policy problem

    zhi
    zhi

    Hi,

    I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • MMU and Cache configuration

    ZbinAhmed
    ZbinAhmed

    Hello there,

    I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.

    I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache

    Steps :

    1.Disable cache, branch predictors

    2. Invalidate…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot!

    sam0220
    sam0220

    when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot!

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • CAT Cache Allocation Technology) and CDP (code and Data Prioritization) features support

    BAUDOUIN
    BAUDOUIN

    Hi,

    XEN 4.7 (last version of Hypervisor Xen) is supporting following cache features:

      - CAT Cache Allocation Technology

      - CDP Code and Data Prioritization

    Those features are supported by x86 L3 caches. This technology seems to improve performances…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv7 CortexA9 Cache Policy - No allocate ?

    josecm
    josecm

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • L2 cache with cortex-A8

    ranchu
    ranchu

    Hello,

    Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ?
    I have some 2 implementation of this routines, one is called L1 and the other L2C-310.

    I am just not sure if using L1 will be good enough, or is it that cortex a8 internal…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache Allocation Technology

    sarbojit
    sarbojit

    Hi guys,

    I have a question regarding "Cache allocation technology" that is present in Broadwell processors of Intel. Does ARM (aarch32/aarch64) support similar way of partitioning the LLC for a process to access?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareability attribute for armv8 cortex a-53

    MarekBykowski
    MarekBykowski

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Data synchronization Barrier and cache.

    Marcin.Kondraciuk@secom.com.pl
    Marcin.Kondraciuk@secom.com.pl

    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before starting copy by DMA, I clean data cache by MVA…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A53 : Cache policy setting

    PrabhuKrishnan
    PrabhuKrishnan

    Hi,

    Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? 

    I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Registers and Cache on M0

    Sean Dunlevy
    Sean Dunlevy

    Hi,
         Coming from a games coder background, I always seek to find the very limits of what a CPU can do. Now we have PragmatIC and very cheap CPUs but much more importantly - vastly cheaper MROM (Mask ROM). With this in mind, I wanted to know how many registers…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
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