Hi

I study coresight test with cortex A53 CPU.

I get FIQ interrupt when I running helloworld test in ini_libc function. But I don't known why.

I use gcc-linaro 4.9 toolchain : aarch64-none-elf-gcc  with glibc 2.14

Set CPU config pin aa64naa32 to 1…

Hello,

I have run two different bare-metal programs on two corresponding ARM cores in Cyclone V (Cortex-A9) in DS5 using JTAG line. The SDRAM is shared between the two cores as is evident from the cache settings which is set to "shared" by default. Core…

Moved to:

https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/43775/shifted-binary-produced-by-arm-none-eabi-objcopy

Hi,

I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

I'm writing bare-metal code, without…

I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).

On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…

Hi everyone,

Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.

In ARM v8 vector table, given on ARMv8-A architecture…

Hi,

I am using ARM cortex A-57 processor and I build image with my own startup code and ld script. The image is loaded with u-boot. When I tried booting the image, it is aborting with following message:

## Booting kernel from Legacy Image at 48080000…