• CNTP_CVAL register write from EL1-NS ("Config-RW")

    armdev
    armdev

    Hi,

    I am trying to setup timer at EL1 level and not able to write to CNTP_CVAL register.

    I would like to know what is the meaning of "Config-RW"  ? It means can be configured ? eg. to be accessed from (NS) EL1 mode ?

    If so what/how to configure…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 backwards compatibility with ARMv7

    Farhan
    Farhan

    Hi there,

    I have been going through a lot of ARMv8 documents, and I have a very basic question:

    -Can I take a Linux Kernel, compiled for a ARMv7 device, and run it on an ARMv8 device in Aarch32 execution mode?

    ( Lets assume that the two SOCs are identical…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • the UART char print in ARM v8-A Foundation Platform

    geekfolk
    geekfolk

    Hi All,

    I am using ARM v8-A Foundation Platform to debug my code. According to user guide, the base address of UART0 in system is 0x1c090000, so I use the following code to try to print a char via UART0:

    *(volatile unsigned char *)(0x1c09000 + offset_of_tx_fifo…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to understand ARMv8 exception level1 secure/non-secure MMU?

    yan.wy
    yan.wy

    Hi Experts,

         ARMv8 MMU TTBRn_ELx registers are banked by exception level.

         In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1

         and Non-secure…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Trusted Firmware, number of cpu cores..

    Anes
    Anes

    Hi all,

    I have two questions about ARM Trusted Firmware. I suppose that I already have answer for one of them..

    1. Does Trusted Operating System (at Secure EL1) use or can use, more than one cpu core, or it always executes on one core?
    2. Does bl31, runtime firmware…
    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to understand ARMv8 'SEVL' instruction in spin-lock?

    yan.wy
    yan.wy

    hi experts,    

        ARMv7 spin-lock use 'WFE' instruction to wait for lock release and use 'SEV' in spin-unlock to notify all cores.   

        but ARMv8 use 'SEVL; WFE' instructions in spin…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Purpose of EL0 EL1 ..

    techguyz
    techguyz

    Hi all,

    ARMV8 has number of exception levels as EL0 , EL1, EL2, EL3 .. How this is managed and what is the exact use case of the same ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Generic Timer - Is it optional?

    techguyz
    techguyz

    Hi all,

    The generic timer feature is provided in the V8 manual. Is it optional like GIC or it will be available with processor IP by default like cache, MPU features. Is it operates on CPU clock or it requires separate clock source ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cryptography instructions sample for ARMv8

    chinatiger
    chinatiger

    hi, experts:

    I found ARMv8 supported some cryptography instructions.

    So:

    Is there any sample code demonstrating how to use these crypto instructions?

    best wishes,

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A, Cavium powering bare-metal servers

    Brian Fuller
    Brian Fuller

    If someone offered to sell your business server-compute cycles for one-tenth the going price, you might think there was a catch. But in this case you’d be wrong.

    Nathan Goulding is the senior vice president of engineering of bare metal server startup…

    • over 4 years ago
    • Processors
    • Processors blog
  • Armv8-A architecture: 2016 additions

    David Brash
    David Brash

    The Armv8-A architecture continues to evolve, with the additions developed through 2016 collectively known as Armv8.3-A. Grouping enhancements in this manner helps the ecosystem manage tools and software support alongside the large numbers of Armv8-A…

    • over 4 years ago
    • Processors
    • Processors blog
  • ISC16 Recap – Fujitsu Takes the Stage

    Darren Cepulis
    Darren Cepulis

    The ISC16 event occurred last week in Frankfurt, Germany. ISC stands for International Super-computing and while ARM is known for its energy-efficient, mobile CPU cores, we are beginning to make some waves in the arena of the world’s largest computers…

    • over 4 years ago
    • Processors
    • Processors blog
  • Semihalf ARM blog #2: Dead board and stack growth

    Rafal Jaworowski
    Rafal Jaworowski

    We’d like to welcome all of you and describe few interesting issues we encounter during our work with ARMv8 and FreeBSD. In this cycle it is planned to talk a little about various bugs found in the kernel and the ways how they were resolved.

    Exception…

    • over 4 years ago
    • Processors
    • Processors blog
  • Introducing Cortex-A32: ARM’s smallest, lowest power ARMv8-A processor

    Kinjal Dave
    Kinjal Dave

    The announcement of the ARM Cortex-A35 processor marked the beginning of a new family of ultra high efficiency application processors from ARM. Today, ARM announced the second member of that family, the Cortex-A32, a new 32-bit processor.

    Highlights of…

    • over 5 years ago
    • Processors
    • Processors blog
  • Armv8-A architecture evolution

    David Brash
    David Brash

    Armv8-A adoption continues to grow as the demand for 64-bit computing gathers momentum. As reported in the Q3-2015 financial results, Arm has now signed a cumulative total of 81 Armv8-A processor and architecture licenses, an increase of 24 licenses in…

    • over 5 years ago
    • Processors
    • Processors blog
  • Programmer's Guide for ARMv8-A

    Michael Thomas
    Michael Thomas
    Following on from the popularity of the Cortex-A Series Programmer’s Guide for ARMv7-A, there is now a programmer's guide for processors implementing the ARMv8-A architecture profile.

    The new Cortex-A Series Programmer's Guide for ARMv8-A…

    • over 5 years ago
    • Processors
    • Processors blog
  • The ARMv8-A architecture and its ongoing development

    David Brash
    David Brash

    ARMv8-A, the ARMv8 A-profile version of the ARM architecture, was first publicly previewed in October 2011. Over the past two years, there have been a growing number of ARMv8-A announcements from ARM, such as its Cortex-A53 and Cortex-A57 products, plus…

    • over 6 years ago
    • Processors
    • Processors blog
  • Critical interrupts

    Michael Williams
    Michael Williams

    In software there are often cases where you need to have critical interrupts serviced. For example, for:

    • Code profiling
    • Kernel debugging
    • Watchdog handling
    • Error handling.

    With the ARMv7-M architecture this can be achieved using nested interrupt handlers, but…

    • over 6 years ago
    • Processors
    • Processors blog
  • ARM Shares Updated Cortex-A53/A57 Performance Expectations

    wangyong
    wangyong
    1.jpg

    With the first Cortex-A53 based SoCs due to ship in the coming months, and Cortex-A57 based designs to follow early next year, ARM gave us a quick update on performance expectations for both cores. Given the timing of both designs we'll see a combination…

    • over 6 years ago
    • Processors
    • Processors blog
  • A Walk Through the Cortex-A Mobile Roadmap

    Brian Jeff
    Brian Jeff

    Chinese Version中文版

    Introduction

    The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one or more of the newer ARM ARM Processors benefit from an…

    • over 7 years ago
    • Processors
    • Processors blog
  • The Top 5 Things to Know about Cortex-A53

    Brian Jeff
    Brian Jeff

    The Arm Cortex-A53 was introduced to the market in October 2012, delivering the Armv8 instruction set and significantly increased performance in a highly efficient power and area footprint. It is available for licensing now, and will be deployed in silicon…

    • over 7 years ago
    • Processors
    • Processors blog
  • High efficiency, midrange or high performance Cortex-A - What is the difference?

    Kinjal Dave
    Kinjal Dave

    A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?

    The simple answer to this is – the power budget…

    • over 7 years ago
    • Processors
    • Processors blog
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