• Virtualizing GICv2.

    Jorge
    Jorge

    Hi all,

    I'm currently virtualizing the GICv2 and some doubts came out during its design. Scenario encompasses the same instance of an hypervisor running in two different CPUs (CPU0 and CPU1). Also, There is one guest running on top of two vCPUs. Each…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    thomas_cp
    thomas_cp

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • armv7a/armv8 : Undefined Abort Exception and MMU

    Vincent Siles
    Vincent Siles

    Hi !

    When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before trying to access the address ?

    Best,

    V.

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8: strongly ordered memory and exclusive access

    Vincent Siles
    Vincent Siles

    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.

    While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • could anybody help me to write a bare metal startup code for LS1043A (ARM V8,A53)in 32bit(AARCH32)mode

    RanadeepReddy
    RanadeepReddy

    excuse me for my English!!!

    i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.

    i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • help me to understand this assembly program for configuring MMU for ArmV8,A53.

    RanadeepReddy
    RanadeepReddy

    ******************************************************************************/
    /*****************************************************************************/
    /**
    * @file translation_table.s
    *
    * @addtogroup a53_32_boot_code
    * @{
    * <h2> translation_table…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A CurrentEL Register Definition

    kuksho
    kuksho

    Where is the register definition of the CurrentEL register ?. I cannot seem to find it in the ARMv8A programming model guide or the Cortex-A53 TRM.

    . How does the PSTATE bits map to CurrentEL ?

    I read somewhere that a CurrentEL value of 0x4 denotes EL1…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Multi core L1 cache coherent

    Jorney
    Jorney

    Dear experts,

     I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.

    Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores  get the right data at VADDR ?

    For…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • indirect branches in ARMv8

    MarekBykowski
    MarekBykowski

    Please clarify that with me... With

    "The current Program Counter (PC) cannot be referred to by number as if part of
    the general register file and therefore cannot be used as the source or destination
    of arithmetic instructions, or as the base, index…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 mmu problem

    bug57520
    bug57520

    Hi ARM experts,

    I have a problem in using armv8 mmu in bare-metal system:

    When using the 4KB translation granule, level 1 table which use D_Block convert VA to 1GB region PA.

    In Armv8 ARM page D4-1744, table lookup starts at level 0.

    Is the Level 0 table…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • which register are dedicated for each MPCore in ARMv8-A architecture?

    StanleyDDD
    StanleyDDD
    Hi  Expert,
    I'm a beginner to ARMv8-A architecture MPcore and now studying A35 MPCore processor documents for low-level software developing.
    One question, when I read DDI0487C_a_armv8_arm and DEN0024A_v8_architecture_PG, from my understanding, there…
    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Feature Comparison ARM v8 series

    techguyz
    techguyz

    Hi Experts,

    Please specify is there any document on the Cortex A series comparison sheet for the various properties.

    For example, Table 2.1 in the https://static.docs.arm.com/den0024/a/DEN0024A_v8_architecture_PG.pdf has details on A53 and A57. Likewise…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Confusion about exception level of ARMv8

    Xinwei
    Xinwei

    Hi,

    I am fairly new to ARM processor and start work with cortexA57 recently.  After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8.

    1. How does the exception level change from one to…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 AArch64: trapping hardware breakpoint to EL2

    meitarb
    meitarb

    Hi everyone!

    I want to set and then trap EL1 hardware breakpoints to EL2. I didn't perfectly understand if such an action is possible at all. In some places the documentation said that MDCR_EL2.TDE enables *Software Breakpoints* trapping to EL2, but on…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What exactly is a full implementation of ARMv8.2-A?

    khunter
    khunter

    The technical spec for ARM Cortex A-75 claims that it supports a full implementation of ARMv8.2-A. The documents I have been able to reference only point to ARMv8A. Specifically I'm looking for what ARMv8.2-A brings to the SIMD table other than fp16 arithmetic…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Updating PC register in aarch64 mode

    PrabhuKrishnan
    PrabhuKrishnan

    Is there a way to update the PC register in the aarch64 mode?

    When we are at aarch32, we can access PC register directly. But in aarch64 mode, there is no handle to PC register.

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MMU - Permission Fault with EL1 access

    maldus
    maldus

    Hello everyone,

    I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal).

    I've successfully setup the page tables for two levels covering…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • dsb and dmb

    digital_kevin
    digital_kevin

    Hi all:

    I have some questions about DMB and DSB in armv8.

    (1)

    In armv8 Reference Manual doc, it says "The DMB instruction does not ensure the completion of any of the memory accesses for which it ensures relative order".

    But in ARM Cortex-A…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Enable MMU and d-cache on ARMv8 for u-boot

    pkumar25
    pkumar25

    Hi,
    This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory. The dump is shown below
    "Synchronous Abort" handler…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A: Virtual to physical translation sometime "fails"

    42Bastian Schick
    42Bastian Schick

    Hi

    I have a strange effect: I need to convert a virtual address to the physical one.

    In the current scenario, I have a 1:1 mapping, so I would not need it, but left the code:

    	mov	x3,x0  // for debug
    	at	S1E1W,x0
    	isb
    	mrs	x1,PAR_EL1
    	mov	x4,x1 /…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • No segmentation fault when expected with aligned load and store

    aketh
    aketh

    Hi all,

    It is a well known fact that performing an aligned vector load with an unaligned memory address should lead to segmentation fault.

    However, when I do try to run code segment below using the same, i do not see any segmentation fault.

    ---------…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • TTBR1 translation fault when using an identity mapping

    maldus
    maldus

    Hello everyone,

    I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3 (Cortex A-53, ARMv8 AArch64).

    The next step I wanted…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Advantage of Zero register over the cost of implementing it ?

    Hpc_me
    Hpc_me

    Hi,

    I've heard that the cost of implementing a register is more.

    In ARMv8 there is a Zero register XZR/WZR, so what is the benefit of implementing such a register over the cost of implementing it?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Arm A-Profile Architecture Developments 2018: Armv8.5-A

    Matthew Gretton-Dann
    Matthew Gretton-Dann

    Working with its architecture licensees and ecosystem partners, Arm continues to evolve its architecture, developing new functionality to meet the needs of both new and existing markets.

    This blog discusses some of the key additions to the A-Profile architecture…

    • over 2 years ago
    • Processors
    • Processors blog
  • Statistical Profiling Extension for ARMv8-A

    Michael Williams
    Michael Williams

    The Statistical Profiling Extension is an optional feature in ARMv8.2. This article will provide an overview of the Extension, describe how it works, and the advantages it provides over other profiling mechanisms.

    Recently, Will Deacon posted a request…

    • over 4 years ago
    • Processors
    • Processors blog
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