• BootROM for A78

    Maunik Patel
    Maunik Patel

    Hi,

    I am planning to boot ARM A-78 core with Linux.
    I have gone through some documents and ended up with below understanding of cortex ARM-A78's boot process:

    ARM A-78 Core Reset => BootROM => 1st stage BootLoader => 2nd stage BootLoader => Kernel …

    • 1 day ago
    • Processors
    • Cortex-A / A-Profile forum
  • Debug Armv8-A alternative in ARM DS

    BL4
    BL4

    Until last year I have been developing small ARM projects (for educational purposes) compiled using the linaro tool chain (GCC 7.5.0 [aarch64-elf])  and debugging in the DS-5 using the

    "Arm Model > Armv8-Ax1 Foundation Platform > Bare Metal Debug >…

    • 1 month ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to understand multi-copy atomicity and who is in charge to maintain this property

    summer123
    summer123

    hi,

    the concept of multi-copy atomicity always troubles me , so could you kindly help to answer the three questions:

    #1 how to understand multi-copy atomicity ?

    #2 who is in charge to maintain multi-copy atomicity in soc system ,interconnect or other components…

    • 1 month ago
    • Processors
    • Cortex-A / A-Profile forum
  • Where can I find "ARMv8 Instruction Set Overview" (PRD03-GENC-010197)

    Senna van Hoek
    Senna van Hoek

    I am trying to prepare a guide for people that want to start programming in A64 assembly and I think the document would be a nice resource.
    It is mentioned in multiple places like here on developer.arm.com but I can only find an old mirror, it is a version…

    • 1 month ago
    • Processors
    • Cortex-A / A-Profile forum
  • Execution stopped in EL3h mode at EL3:0x0000000000000200

    dak.sera
    dak.sera

    Hi,

    Cortex A53 FVP debug connection get stuck with the following. It doesn't run beyond this point.

    Execution stopped in EL3h mode at EL3:0x0000000000000200
    In __push_back_slow_path<const unsigned char &> (no debug info)
    EL3:0x0000000000000200…

    • 2 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Data Cache Zero by Virtual Address (DC ZVA) instruction

    Frederick
    Frederick

    HI Everyone,

    i have been trying to test whether or not DC ZVA instruction causes an L1 or L2 cache allocation on Cortex-A73.

    The ARMv8-A architecture reference manual makes no statements about whether or not the DC ZVA instruction causes allocation to…

    • 2 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • why output of rndr instruction is mixed with bootloader's entropy to form linux kaslr on arm64

    scopichmu
    scopichmu

    It is code snippet from Linux kernel (arch/arm64/kernel/kaslr.c) how kaslr seeed is obtained:

    u64 __init kaslr_early_init(u64 dt_phys)
    {
          ...
    
            /*
             * Retrieve (and wipe) the seed from the FDT
             */
            seed…

    • 2 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Programming for Aarch64

    afernandezody
    afernandezody

    Hello,
    I've been reading some of the documentation for Aarch64 and have a couple of questions about programming. The architecture reference manual contains plenty of up to date information but it's not exactly a five-minute read. On the other hand, the…

    • 2 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMV8 multithread

    Rifakst
    Rifakst

    I want to know if with the ARMV8 architecture in SMP mode I can create thereads and associate each thread with a core.
    for example I want to create a thread 1 which contains an X function and I want this function executed on core 3.

    • 2 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM cortex A53 PMU read from another core

    Nikos Pol
    Nikos Pol

    Hello.

    I would like to ask if it is possible to read the PMU of core0 from core1.

    So far i have work with an one core CPU and i use the MRS, MSR instructions to set the PMU.

    How to enable the PMUs for each core?

    Also, i read the PMUs are memory mapped…

    • 2 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?

    George_
    George_

    Hello:

    Suppose all exception Ievels support both big and little endian operation. According to the ARMv8 ARMARM, when exception taken from AArch32 state, the SPSR_EL1.E bit can control the endianess on executing an exception return operation in EL1, which…

    • Answered
    • 3 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Rowhammer bug on ARM

    Frederick
    Frederick

    Is there anyone who is working or having background knowledge on the rowhammer bug on ARM-based devices ?

    Thank you.

    • 3 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Parallel heterogenous computing for IoT-boards and nanocomputers with Armv8 and AArch64 hardware architecture

    Arthur Ratz
    Arthur Ratz
    This is a guest blog contribution from Arthur Ratz

    Build and run a modern parallel code in C++17 and CL and SYCL programming model specification on the IoT-boards and innovative tiny-sized nanocomputers. These are based on the revolutionary cluster…

    • 3 months ago
    • Processors
    • Processors blog
  • How can I trigger an SError exception on a cortex A processor

    Awax
    Awax

    Is there a reproducible way of intentionnaly triggering a SError on a cortex A implementation (CortexA53 for example),
    I need this to implement handlers for different errors and I need this to test my implementation.

    THanks.

    • 3 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Disable Cache L1 et L2 Armv8

    Rifakst
    Rifakst

    Hi

    I work with the ARMV8 architecture, I want to disactivate L1 cache ,

    to disable the L1 cache I found in the user manual
    "" The SCTLR.I bit enables or disables the L1 instruction cache. ""

    my question here is: I did not find in the…

    • Answered
    • 3 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to disable the branch prediction on armv8

    Rifakst
    Rifakst

    Hello,

    I am working with ARMV8 Cortex A72 architecture,
    i want to know can i turn off branch prediction?
    and how can i do it?

    best regards,

    • 3 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Arm A-Profile Architecture Developments 2020

    Martin Weidmann
    Martin Weidmann

    Working with its architecture licensees and ecosystem partners, Arm continues to evolve its architecture, developing new functionality to meet the needs of both new and existing markets.

    This blog discusses some of the key additions to the A-profile architecture…

    • 5 months ago
    • Processors
    • Processors blog
  • How to set up stage-2 translation table

    irakatz
    irakatz

    Hi,

    I am trying to enable stage-2 translation for Armv8 aarch32, cortex-a53. If I set HCR.VM=1(enable stage-2 translation) it will crash. I suspect it does not set up stage-2 translation table. But when I read the Arm Architecture Reference Manual, I…

    • Answered
    • 6 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • DRAM address mapping on a Cortex-A72 ARMv8

    Frederick
    Frederick

    HI Everyone,

    I need help about DRAM address mapping on a Cortex A-72 especially my question is : given two physical memory addresses how can i know if they are in the same DIMM, Rank and Bank ?
    is there any bit to check for it ?

    Thank you.

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Core_n System Timer reset behaviour

    Helmy Mohamed
    Helmy Mohamed

    Hello, 

    I'm working with i.MX8DX (Dual Core CortexA35) 

    My question is this:

    If a PE is reset. Is the CNTPCT_EL0 is also reset and start from 0? or keep counting normally?

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • How Can I Synchronize the Generic Timer values in different PEs in the same Core?

    Helmy Mohamed
    Helmy Mohamed

    Is the timer values in CNTPCT_EL0 in each PE in the same core are synchronized? and if not how can I do so?

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Time measurements ARM v8 platform running Linux

    Frederick
    Frederick

    HI Everyone,

    This is my first time here.

    I need help about time measurements on a Cortex-A72 (Arm v8) 64-bit.

    I have been trying to read the cycle counter (i have got root privileges on machine), but i can't.

    my c code:

    #define _GNU_SOURCE
    #include…

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • trustzone memory configuration for cortex-A57

    raks8877
    raks8877

    Hello,

    I am using jetson tx2 development board which has arm cortex a57 processor which uses arm trusted firmware(atf) to boot. Trusty is the secure world operating system provided by atf.

    Following are my questions:

    1) How to configure how much ram…

    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Neoverse N1 microarchitecture ISA support

    Mohannad Ismail
    Mohannad Ismail

    Greetings,

    I have a few questions regarding the Neoverse N1. According to the specifications, it mainly uses the ARMV8.2 ISA. However, there is possible support also for other instructions in other ISAs such as v8.4, v8.5 and cryptographic extensions…

    • Answered
    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • translation table APTable permission problem

    raks8877
    raks8877

    Hello,

    I am trying to make pmd level of the translation table as read only so that any writes in the pte entries should cause a permission fault.

    Current steps which i am doing are:

    1) inside kernel space, allocating 2 pointers (say p, q) and allocating…

    • 8 months ago
    • Processors
    • Cortex-A / A-Profile forum
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