Hello,
I'm using an ARMv8 processor in 32 bit ARMv7 compatibility mode.
I would like to know if there is any difference (performance gain) in ARMv8 running in AArch32 mode Vs running the same on an an ARMv7.
Thanks!
Hello,
I'm using an ARMv8 processor in 32 bit ARMv7 compatibility mode.
I would like to know if there is any difference (performance gain) in ARMv8 running in AArch32 mode Vs running the same on an an ARMv7.
Thanks!
Hi,
I am using ARM cortex A-57 processor and I build image with my own startup code and ld script. The image is loaded with u-boot. When I tried booting the image, it is aborting with following message:
## Booting kernel from Legacy Image at 48080000…
Hi Fellows,
I want to determine in code, if the processor is in EL0 mode or not. I read CurrentEL register to do this but if my code is running from EL0, it throws an exception since we can't access CurrentEL from EL0. Is there any alternative and easy…
Hi Fellows,
I want to switch stack pointer to SP0 from SP1 every time an exception is taken to EL1 on armv8. I execute MSR SPSel, #0 to do this. My question is that is it necessary to use an ISB intruction etc. after it? If yes, what are the performance…
This is sort of intriguing for me. I couldn't find any saturation instructions using general purpose register in ARMv8. However, there are saturation instructions for Neon registers I couldn't find the same involving general purpose register. Can anyone…
Hello,
I would be interested to try the new features of the ARMv8-M architecture, in particular v8-M TrustZone, but I can't find necessary tools in order to do so.
1. I need a toolchain that supports the new instructions introduced with v8-M (SG, BXNS…
I was going through the ARMv8 Architecture Reference Manual and I came to know that it does not support many instructions that were previously supported by ARMv7 architecture. For example ARMv8 does not support conditional codes and have a seperate instruction…
Hi ,
I am running aarch32 app in ARMv8a( cortex-a57 ) device. The performance reports ( using gettimeofday() utility ), showing large spikes on random calls. But the same app on ARMv7a( cortex-a15 ) device is quite stable.
Will the aarch32 library…
Hi, ARM experts:
I found there are some crypto instructions in v8 Arch, they use register Vn.
Does these operations own a secure property, i.e. how to ensure non-secure world can not visit or dump some secure information?
Steven…
hi experts,
ARMv7 spin-lock use 'WFE' instruction to wait for lock release and use 'SEV' in spin-unlock to notify all cores.
but ARMv8 use 'SEVL; WFE' instructions in spin…
hi experts,
I am studying the ARMv8 exception levels. I have a question about ELs.
EL1 is described to run OS kernel and EL0 is application level.
The exception levels change only occur on exception or exception return.
In ARMv7, the instruction…
I find an event "Real-Time & Embedded Computing Conference (RTECC)" from ARM official website. ARM will introduce The ARM Processor Roadmap Deciphered including Cortex-A56 (64-bit) in this event. Considering next generation ARMv8 64-bit…
Hi experts,
I have tried to configure the attribute of one memory region not able to be write in secure world and then try to write data into this region.
What I expect is that there will be an exception raising after write data into this region. But what…
Hello everyone,
I hope to find some assembly language examples of ARMv8 AArch64 instruction set.
Where can I find them?
Thank you in advance !
I am interested in buying a Juno development board, but have a set of technical questions related to the platform, namely:
(1) What are the migration modes that are available on the ARMv8 big.LITTLE? In particular, can I use both Cluster and Global…
Hi all,
The main differences in ARMv8 EL3 is that it has its own MMU and it can only be entered via SMC and exit via ERET instruction. ERET instruction reads from ELR_EL3 (Exception Link register) and continue execution from that address (of course changing…
Hi,
I'm working on a project which is for debugging cortex-a53 through Jtag interface.
The Jtag clock TCK is set to 300kHz which is pretty low, and I can properly read back debug registers such as EDSCR and EDPRSR. EDPRSR is 1 before I issue the 'halt…
Hi all,
Is there any document related to the branch predictor algorithm utilized in the ARMV7 and ARMV8 and how the software (ABI) can be aptly developed ac-complying the same ?
Hi all,
There is a dedicated register for store and restoring the OS thread context informations in ARMV8. What is the advantage of it and what is the use case of the same ??
Hi all,
The new core ARM V8 supports A & R series alone M series are also be released in near future ?
If not why ?
Hello,
I want to experiment with a storage solution ARM based. Is there any provider actually selling dev kits or consumer boards based on ARM Cortex-A53 or ARM Cortex-A57?
Obviously the main requirement for purchase is the availability of SATA3 ports for…
Hi all,
ARMV8 has number of exception levels as EL0 , EL1, EL2, EL3 .. How this is managed and what is the exact use case of the same ?
Hi all,
The generic timer feature is provided in the V8 manual. Is it optional like GIC or it will be available with processor IP by default like cache, MPU features. Is it operates on CPU clock or it requires separate clock source ?
Hi all,
In ARMv-7 the co-processor register is used to configure the TCM, cache, MMU, MPU, etc.
In ARMv-8 the co-processor logic is removed and integrated as the system register. Is there any performance difference by doing that ?
Hi all,
Kindly suggest some logical code to realize the gathering and re-ordering attribute in the ARMv8. How this attribute can be best utilized for actual use case scenarios ?