• DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

    Trampas
    Trampas

    I have been reading through the ARM documentation on memory and instruction barriers. 

    I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

    I have also read the same about…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When an exception is taken into account

    Karolis
    Karolis

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • DWT

    Gabor M.
    Gabor M.

    Hello,

    I use DWT in Cortex-M4 to catch instructions that write or read memory contents and the problem is it doesn't stop immediately where I expect, it stops after 2-3 instruction later than where it should and the contents of registers are overwritten…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Can't understand the difference between armv7e-m and armv7e-m-pic?

    Bilal Wasim
    Bilal Wasim

    Hello people. I'm trying to do libgcc extraction for hard FPU's for k70 tower board. However, when I look at the libgcc library for arm targets, I find armv7-m, armv7e-m and armv7e-m-pic. I'm able to deduce from the armv7-m reference manual that the difference…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When an exception is taken into account

    Karolis
    Karolis

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Is a DMB required between loading BASEPRI and storing BASEPRI_MAX?

    Ramzyo
    Ramzyo

    Hi,

    I have a question regarding BASEPRI, BASEPRI_MAX, and DMBs as they relate to both the V7-M and V7E-M architectures.

    Let's say I have the following assembly,

    // stuff
    mrs r0, BASEPRI
    msr BASEPRI_MAX, #3
    // more stuff

    Is it necessary to put a…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • M4 Assembly - Set Enable also enables the Clear Enable Interrupt Register

    marcusob
    marcusob

    Hi,

    I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Present program counter address

    Karolis
    Karolis

    Good day,

    I want to refresh and (or) update my knowledge on ARMv7.

    Is it true for ARMv7-M that when CPU starts execute one instruction, PC value has already been updated/is being updated in parallel with address of the next instruction? Or PC is updated…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARMv7-M: Question about syn/asynchronous exception?

    yenWu
    yenWu

    Hi all,

    I have little experience with bare metal programming at STM32 series and currently studying exception behavior in "ARMv-7m Architecture Reference Manual".

    I'm confused about syn/asynchronous exception at B1-569. I have one question about…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Is ARMv7-M3 thumb instructions compatible to ARMv7-A thumb?

    Kaiyuan
    Kaiyuan

    Hello guys,

    I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA.

    Is ARMv7-M3 instructions compatible to ARMv7-A, especially thumb instructions?

    Thank you very much.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What is the meaning of a 64 bit aligned stack pointer address?

    Murtuza Quaizar
    Murtuza Quaizar

    According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in  it says:

    "Although the processor hardware allows SP to be at any word aligned address at function boundaries, standard programming practice…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Updated ARMv7-M architecture reference manual for Cortex-M7 ?

    Paul Stoffregen
    Paul Stoffregen

    Has an updated v7m architecture reference been published yet?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Critical interrupts

    Michael Williams
    Michael Williams

    In software there are often cases where you need to have critical interrupts serviced. For example, for:

    • Code profiling
    • Kernel debugging
    • Watchdog handling
    • Error handling.

    With the ARMv7-M architecture this can be achieved using nested interrupt handlers, but…

    • over 6 years ago
    • Processors
    • Processors blog
  • ARMv6-M vs ARMv7-M - Unpacking the Microcontrollers

    Chris Shore
    Chris Shore

    This article is a follow-on to Navigating the Cortex Maze. As a high-level overview, the earlier article provides an easy way-in to the ARM processor range. It covers Cortex-A (architecture ARMv7-A), Cortex-R (ARMv7-R) and Cortex-M (ARMv7-M).

    But the…

    • over 7 years ago
    • Processors
    • Processors blog
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