• Question about LPAE(Large Physical Address Extensions) for ARMv7

    uncontested
    uncontested

    I read the ARMv7 architecture reference manuals. The spec. says LPAE allows 32-bits VA to be translated into 40-bits PA. The 40-bits PA means the width of address bus is 40-bits or greater than 40 bits, is it true? So my first question is what the width…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv7-a MPU/PMSA - Unified Region (Base/Size) question

    Dyntaos
    Dyntaos

    Hello,

    I have been reading and searching for some time and have learned a lot about the MPU on an ARMv7-a. I am attempting to use the Unified Region Base/Size registers to both limit memory access, but also have the "Base" value added to memory references…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • armv7a/armv8 : Undefined Abort Exception and MMU

    Vincent Siles
    Vincent Siles

    Hi !

    When MMU is enabled, and a undefined abort exception is triggered, are we sure that the address stored in the `lr` / `elr_elx` registers is actually mapped by the MMU, or should I check that before trying to access the address ?

    Best,

    V.

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Instruction format in documentation ARM-v7-A

    Muhui
    Muhui

    Hi. This is the first time to ask questions in this forum. Hope this is the right place to reach you and get help.

    I refer to the documentation ARMv7-A and ARMv7-R edition

    I don't understand the brackets() in the instruction details.

     For example,…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Arm Technical Training – Any time, any place

    Matt_Rushton
    Matt_Rushton

    Partner Training at Arm has been a great success over the last 15 years. It has expanded the knowledge and capabilities of our Partners’ Engineering teams by delivering classroom sessions to over 4000 attendees in 2016 alone and has helped our Partners…

    • over 2 years ago
    • Processors
    • Processors blog
  • Different performance in HYP and SVC mode ARMv7A?

    ivanpavic
    ivanpavic

    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is ARMv7-M3 thumb instructions compatible to ARMv7-A thumb?

    Kaiyuan
    Kaiyuan

    Hello guys,

    I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA.

    Is ARMv7-M3 instructions compatible to ARMv7-A, especially thumb instructions?

    Thank you very much.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • MIPS Calculation on ARMv7

    Sridhar Artham
    Sridhar Artham

    Hi All,

    I want to measure MIPS(Million Instruction per second, i.e. instruction count per second) on ARMv7 Platforms. What is the procedure for calculating MIPS for ARMv7 platforms?

    Thanks and Regards

    Sridhar Artham

    • Answered
    • over 4 years ago
    • Processors
    • Classic processors forum
  • Can we use PMU(Performance Measuring Unit) on Cortex A8 for calculating cycles on Simulator without hardware?

    Sridhar Artham
    Sridhar Artham

    ARMv7A family members will have PMU on the processor. Using this PMU, we can access cycle counts. Can we relay on this using the simulator?

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Dhrystone Testing on Cortex A9: disabling Prints increases the DMIPS.

    anoop
    anoop

    i am seeing an issue while doing Dhrystone test. i am using Dhrstone source code of version 2.1.

    when i run this source code on LINUX platform, i got DMIPS/MHz =1.6

    but there are some printing commands that prints variables used, when i disable them i got…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • I cannot write the sp register in the monitor mode

    Takumi Shimada
    Takumi Shimada

    I use a Cortex-A7 board and write start up code.

    I try to use Security Extension.

    I use `smc` instruction and make cpu mode monitor mode.

    In the monitor handler, I tried to changed stack pointer value for calling other functions.

    But after execute `ldr sp…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • updating CPSR in USER UNPRIVILEGED mode

    anoop
    anoop

    as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is user mode, since user mode is unpriviliged so i must…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv7 architecture

    Harikrishna Sola
    Harikrishna Sola

    Can anyone share the ARMv7 architecture document to download ?

    - Hari.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9: Eviction of dirty line from the region marked as Only "Inner Cacheable" from L1 cache - will if be allocated into L2?

    Hemant
    Hemant

    Hello,

    Consider following scenario:

    1. A 4 KB page starting @0x80000000 is marked as Normal Memory, Inner Cacheable, write-back, non-shareable, non-outer cacheable, L2 is inclusive cache.
    2. Now, the s/w writes to the first word in the page. Let's assume valid…
    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Compability between architecture ARMv5TE and ARMv7-A

    Holger Elsenheimer
    Holger Elsenheimer

    Hello everyone!

    I have a question about the compability between architecture ARMv5TE and ARMv7-A.

    We want to change our Platform-Processor from ARM 946E-S to an ARM Cortex A9.

    The Problem is, that our customers have written own programs in IEC 61131 (PLC…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to compile with gcc toolchain that uses ARM neon instructions

    Haris
    Haris

    Hi,

    I would like to ask which version of gcc and with what flags , may I compile some c code to assembly code that uses arm neon coprocessor for ARMV7-A processor. Of course I want to use the processor itself but also the coprocessor. Is this gcc optimal…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Security Extensions in ARMv7

    Rakesh Reddy
    Rakesh Reddy

    "the Security Extensions integrate hardware security features into the architecture". Please can anybody make clear what exactly is "security" in hardware point of view in an ARMv7-A profile..?

    can you please give any real-time example…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • range of BL instruction in arm state

    BASIL BABY
    BASIL BABY

    range of BL instruction in arm state is + or - 32MB as per instruction set.how...........?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Shares Updated Cortex-A53/A57 Performance Expectations

    wangyong
    wangyong
    1.jpg

    With the first Cortex-A53 based SoCs due to ship in the coming months, and Cortex-A57 based designs to follow early next year, ARM gave us a quick update on performance expectations for both cores. Given the timing of both designs we'll see a combination…

    • over 6 years ago
    • Processors
    • Processors blog
  • New version of the Cortex-A Series Programmer's Guide is Available

    Michael Thomas
    Michael Thomas

    The ARM® Cortex®-A Series Programmer’s Guide has proved to be a very popular addition to the ARM documentation set, and now also forms the reference textbook for the ARM Accredited Engineer(AAE) examinations.

    The updated ARM® Cortex®-A…

    • over 6 years ago
    • Processors
    • Processors blog
  • Five things you didn't know about the ARM® Cortex®-A15 Processor

    Bernard Ortiz de Montellano
    Bernard Ortiz de Montellano

    By now, everyone knows that the ARM Cortex-A15 processor is ARM’s highest performance v7a ARM core to date. The Cortex-A15, along with the other ARM-based cores, are helping tablets surge a projected 53.4% this year, and has been part of some flagship…

    • over 6 years ago
    • Processors
    • Processors blog
  • A Walk Through the Cortex-A Mobile Roadmap

    Brian Jeff
    Brian Jeff

    Chinese Version中文版

    Introduction

    The ARM Cortex-A mobile application processor product line spans several generations and three main product tiers. Developers and SoC designers experienced with one or more of the newer ARM ARM Processors benefit from an…

    • over 7 years ago
    • Processors
    • Processors blog
  • High efficiency, midrange or high performance Cortex-A - What is the difference?

    Kinjal Dave
    Kinjal Dave

    A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?

    The simple answer to this is – the power budget…

    • over 7 years ago
    • Processors
    • Processors blog
  • Continuing the journey through the Cortex maze...

    Chris Shore
    Chris Shore

    Following on from two earlier articles (Navigating the Cortex Maze and ARMv6-M vs ARMv7-M - Unpacking the Microcontrollers), you might be interested in a new piece on the ARMv7-A architecture and Cortex-A series (ARMv7-A - Power to the People). I hope…

    • over 7 years ago
    • Processors
    • Processors blog
  • The Top 5 Things to Know about Cortex-A7

    Kinjal Dave
    Kinjal Dave

    The ARM Cortex-A7 MPCore processor is the most energy efficient application processor that ARM has ever developed and has dramatically extended ARM’s low-power leadership in entry level smart phones, tablets and other high end mobile devices.  Here…

    • over 7 years ago
    • Processors
    • Processors blog
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