• How to schedule Secure/Normal kernels in TrustZone implementation?

    Kaiyuan
    Kaiyuan

    I read TZ whitepaper. TZ's software architecture includes normal OS, secure OS, and a monitor that manages switching between two OS. The notion is clear. But how to implement them confuses me.

    Running and managing two kernels on a SoC needs mechanism…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can anyone provide an example of asynchronous exceptions?

    Jay Zhao
    Jay Zhao

    Below is from ARMv7 Architecture doc.

              An exception is described as asynchronous if either of the following applies:
              — the exception is not generated as a result of direct execution or attempted…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why the different encodings?

    Juha Aaltonen
    Juha Aaltonen

    Why are there different encodings of instructions?

    What's the idea/background/etc for their co-existence?

    Can different encodings be mixed in the code? (Not ARM encodings with Thumb encodings- without ARM/Thumb mode change,

    but, like A1 and A2 or T1…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The merit of data cache cleaning

    Henry Choi
    Henry Choi

    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • system requirements

    SGR
    SGR

    what are the minimum hardware requirements to setup wifi on arm-7 processors.

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What are hints?

    Juha Aaltonen
    Juha Aaltonen

    What does it mean that an instruction is a hint instruction, like NOP, YIELD and WFE?

    I haven't found any explanations in ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, Issue C.

    [EDIT]

    Aha, this has already been answered in:

    Are…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • MRS/MSR (Banked register)

    Juha Aaltonen
    Juha Aaltonen

    What can be accessed by MRS/MSR in user mode?

    In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

    B9.3.10      MSR (Banked register)
    cond  0 0 0 1 0 R 0 0        M1      …
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9/GIC: de-activate an active interrupt

    42Bastian
    42Bastian

    Hi

    my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world.

    No the problem: If the normal-world error happens in an…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • About PL310 cache controller and data aborts

    Niranjan Dighe
    Niranjan Dighe

    Hello All,

    I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know a few things (which are not very clear in the TRM…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • UPREDICTABLE instructions

    Juha Aaltonen
    Juha Aaltonen

    Any idea about instructions marked as UNPREDICTABLE: can it then be UNDEFINED?

    In other words: UNDEFINED REQUIRES the instruction to cause UND-exception, but

    MAY UNPREDICTABLE do that, or does it have to execute normally except that the result may be…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Still more stupid questions on Cortex-A7 instruction set

    Juha Aaltonen
    Juha Aaltonen

    I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found

    an answer to in ARMv7-A/R ARM Issue C.

    How is this special?

    LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD<c>_<Rt>,_<Rt2>,_[PC,_#-0]_Special_case…
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What does this instruction do?

    Juha Aaltonen
    Juha Aaltonen

    In the ARMv7-A/R ARM Issue C I found two instructions with odd encoding: PUSH and POP, encoding A2.

    What's the Rt's role? I guess Rt and 'registers'-bitlist needs to match?

    Encoding A2 ARMv4*, ARMv5T*, ARMv6*, ARMv7

    PUSH<c> <registers>…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Address Space Identifier - ASID

    Mike Clark
    Mike Clark

    For ARMv7 -A/R systems, the MMU uses an ASID to distinguish between memory pages which have the same virtual address, but which are used by an individual task ( I.e. A task which uses non-Global memory). The ASID is an eight-bit value, from 0-255, assigned…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Questions about Generic Timer in ARMv8

    wangchj
    wangchj

    When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

    But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

    And, if…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Context ID Register & Process Context Switch

    onion
    onion

    Hi, all

    What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value

    of Process ID and ASID? As far as I know, it is so in Linux. Is that the same in the other OSes?

    Is it essential to deal with ASID if…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Funny asymmetry with banked register names

    Juha Aaltonen
    Juha Aaltonen

    Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but

    one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.

    In document (ARMv7-A/R ARM Issue…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

    Yeo Reum Yun
    Yeo Reum Yun

    Hi Experts,

    I'm reading white paper for ARMv7 and ARMv8.

    but when i reading cache part and memory re-ordering, i have silly questions.....

    Suppose there are below instructions..

     

    Core A:

         STR R0, [Msg]

         STR R1, [Something…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does load/store-exclusive violate Hypervisor Transparency?

    Jan Teske
    Jan Teske

    Hello Community,

    I am currently learning hypervisor design using ARM's virtualization extensions (on both ARMv7 and ARMv8).

    A note in the ARMv8-A reference manual (section D1.5) mentions:

    "In some systems, a Guest OS is unaware that it is running on…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Return address from FIQ_Handler. Do we come back to the next instruction?

    Harshdeep
    Harshdeep

    Is it

    MOVS pc, r14

    or

    SUBS pc, r14, #4

    This is written in the ARMDEN0013D. but in the table it says next instruction whereas the SUBS pc, r14, #4 means the instruction which was interrupted.

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • From the CPU's point of view, how does it distinguish an assembly code is an ARM code or a Thumb code?

    Kun.Niu
    Kun.Niu

    From the CPU's point of view, how does it distinguish an assembly code is an ARM code or a Thumb code?

    Is there some signal bit represent the code is ARM or Thumb code, this is just my guess.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • shareable attribute in armv8

    Harish G
    Harish G

    Hi Experts,

                        I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different.

    I could…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

    Christian Ascheberg
    Christian Ascheberg

    Hello,

    I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Feature wise comparision for Cortex A series processors

    techguyz
    techguyz

    Hi Experts,

    Is there any document on feature wise comparison chart on the Cortex A series of processors ?

    Like,

    Cache for Cortex A8/9/52...

    MMU for cortex A8/9/52..

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • indicator for A core system timer implemented or not

    hostia
    hostia

    Hi ARM expert,

        In ARM V7 RM, I saw "This chapter describes the implementation of the ARM Generic Timer as an OPTIONAL extension to an ARMv7-A or ARMv7-R processor implementation.". So, I think it means that a SoC implementation…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to understand SDIV instruction availability?

    Robert
    Robert

    Hi,

    When I read Thumb-2 instruction manual, it is not clear to me about SDIV availability. Especially I do not understand the last line "are not available in ARM state."

    Could you explain it to me?

    Thanks,

    New functionality introduced with Thumb…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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