• Getting started with AMBA and AMBA AXI

    NickT
    NickT

    As you may be aware, far from being a misspelled fossilized tree resin, AMBA is a freely available open standard for the connection and management of functional blocks in a system-on-chip (SoC). Since the mid-90s, AMBA has been implemented by vendors…

    • 8 months ago
    • Processors
    • Processors blog
  • New Arm online training course: Introduction to the AMBA ACE protocol

    NickT
    NickT

    Arm is pleased to announce a new online training topic - An introduction to the AMBA ACE protocol.

    About the course

    This training topic covers essential information on Arm’s AMBA ACE protocol. Hardware system-level coherency enables the sharing of…

    • over 1 year ago
    • Processors
    • Processors blog
  • AMBA

    VT
    VT

    Hello....!!!

    Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Bare Metal Input/Output - Documentation?

    Mike Clark
    Mike Clark

    Does anyone know of an Idiot's Guide to this topic? In particular, how does a processor with no special I/O instructions issue a request, e.g. to a serial output device to output "Hello, World"? And how does Memory-Mapped I/O work in detail? Where is…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI4: Wider transactions than BUS width allowed?

    Robert Schilling
    Robert Schilling

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder Register Slice of AMBA 3.0 AXI

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    Recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.


    Register slice is described in AMBA 3.0 AXI.

    "This makes…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA AXI :Unaligned "INCR" data transfer

    Kousik
    Kousik

    Hi,

        i am confusing in the following point ,with an example....

       if

         Start_Address = 23

         Number_Bytes = 8

         Burst_Length   = 8

         data_Bus_Byte…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI4 Lite handshake

    Long John
    Long John

    Hi,

    in the AMBA/AXI Protocol specification, I read

    There must be no combinatorial paths between input and output signals on both master and slave interfaces.

    What signals, explicitly, may not have combinatorials between them?

    Thanks in advance.

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI Locked Write and Lock Scope

    Deepak Ameta
    Deepak Ameta

    Hi All,

           1)  1st master is doing locked write transfer to 'X location after that, Can 2nd master initiate a read normal transfer for 'Y address in same slave? . And still unlocked transfer is not initiated by the 1st master?.…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    sourav
    sourav

    AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    Kun.Niu
    Kun.Niu

    AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?

    Kun.Niu
    Kun.Niu

    In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA3 AXI - Exclusive access

    Cao Phi Ho
    Cao Phi Ho

    1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location??

    Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID (first is 00 and second is 01) to the sam an address…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA3 AXI Relationship Between Channels

    Cao Phi Ho
    Cao Phi Ho

    In the document AMBA3 AXI (3.2 Relationships between the channels)

         Two relationships that must be maintained are:

              • read data must always follow the address to which the data relates…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • PLEASE HELP ME (AMBA3 AXI)

    Cao Phi Ho
    Cao Phi Ho

    1/ WHY "the width of the ID field at a slave interface is wider than the ID field at a master

    interface"??? Can you please explain in more detail the reason???

    2/ Do AXI protocol have support "read interleaving"???

    Thanks you so much…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Please help about AMBA AXI 3.0

    Kiêm Nhật Minh
    Kiêm Nhật Minh

    I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0

    1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?

    2. In the FIXED…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder AMBA 3.0 AXI difference of data interleaving and write data interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.



    as you can see the first picture, slave send the read…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. amba 3.0 axi interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.


    i wonder about interleaving and out-of order.

    AXI supports…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder AMBA 3.0 AXI out-of order - WID & RID

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.

    Firstly, i very wonder AWID, WID and BID when write transaction…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder AMBA 3.0 AXI handshake

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

       

    firstly, i very wonder the handshake…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Reason for having decouple write address, data channels in AXI4

    Naveen
    Naveen

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Question for AXI responce when access error

    Jun Usami
    Jun Usami

    HI,

    Does anyone know the minimum number of error responce (wready & rvalid) when AxLEN = 15?

    Does it need to respond 16th? or we can respond 1 only?

    Regards,

    -GARO

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • About AXI4 address channel and data channel handshake sequence

    田永丰
    田永丰

    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

    For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

    Remark:

    Just now, I noticed that…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Significance of the WVALID signal in AXI

    Ronnie Dominic Joseph
    Ronnie Dominic Joseph

    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI FIXED burst ; Wr/Rd narrow transactions.

    Tsach
    Tsach

    1. I'm examining AXI burst of FIXED type.

    2. Data bus width is of 128bit.

    3. case scenario WRITE:

        awlen    = 2 (3 write transfers)

        awsize  = 2 (32bit per each transfer)

        awburst = 0 (FIXED)…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
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