• How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

    zynq
    zynq

    hey,

    How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

    in baremental driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x00,

    but in linux driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x01,

    can anybody tell me…

    • Answered
    • over 4 years ago
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  • Cortex-A9-PL310 AXI connection

    Luke
    Luke

    Hi experts,

    I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller.

    I think Figure 1.2 in the TRM is a good starting point:

    CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 1.2. Typical…

    • Answered
    • over 5 years ago
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  • AXI Atomic Access

    Deepak
    Deepak

    Hello,

    I don't know whether this question has been asked or not. If yes please direct me to the appropriate discussion.

    My question is:

    1. Suppose there are two masters, M0, M1 and one slave, S0. M0 initiates an Exclusive access to S0 and gets the response…

    • Answered
    • over 5 years ago
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  • Question on how to calculate the axi read time

    redbud
    redbud


    Hello,

    I have a question on axi read time. If we have 20 read commands, the read outstanding is 4 and read latency is 500ns, how much time is needed to read all of these data back?

    I feel puzzled on this for a long time and I need a relatively accurate…

    • Answered
    • over 5 years ago
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  • AXI Locked Write and Lock Scope

    Deepak Ameta
    Deepak Ameta

    Hi All,

           1)  1st master is doing locked write transfer to 'X location after that, Can 2nd master initiate a read normal transfer for 'Y address in same slave? . And still unlocked transfer is not initiated by the 1st master?.…

    • Answered
    • over 5 years ago
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  • AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    sourav
    sourav

    AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    • Answered
    • over 5 years ago
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  • AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    Kun.Niu
    Kun.Niu

    AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer…

    • Answered
    • over 5 years ago
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  • In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?

    Kun.Niu
    Kun.Niu

    In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?

    • Answered
    • over 5 years ago
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  • AMBA3 AXI - Exclusive access - 04/16/2015

    Cao Phi Ho
    Cao Phi Ho

    In document on AXI3:

    "The exclusive access monitor records the address and ARID value of any exclusive read

    operation. Then it monitors that location until either a write occurs to that location or

    until another exclusive read with the same ARID value…

    • over 5 years ago
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  • AMBA3 AXI - Exclusive access

    Cao Phi Ho
    Cao Phi Ho

    1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location??

    Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID (first is 00 and second is 01) to the sam an address…

    • Answered
    • over 5 years ago
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  • AMBA3 AXI Relationship Between Channels

    Cao Phi Ho
    Cao Phi Ho

    In the document AMBA3 AXI (3.2 Relationships between the channels)

         Two relationships that must be maintained are:

              • read data must always follow the address to which the data relates…

    • Answered
    • over 5 years ago
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  • PLEASE HELP ME (AMBA3 AXI)

    Cao Phi Ho
    Cao Phi Ho

    1/ WHY "the width of the ID field at a slave interface is wider than the ID field at a master

    interface"??? Can you please explain in more detail the reason???

    2/ Do AXI protocol have support "read interleaving"???

    Thanks you so much…

    • Answered
    • over 5 years ago
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  • Please help about AMBA AXI 3.0

    Kiêm Nhật Minh
    Kiêm Nhật Minh

    I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0

    1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?

    2. In the FIXED…

    • Answered
    • over 5 years ago
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  • AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

    Martin Trummer
    Martin Trummer

    Hi guys,

    I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.

    First consider an unaligned access on address 0x1.

    Can this access be created in 2 ways?

    1) Addr=0x0, Wrstrb=1110

    2) Addr=0x1, Wrstrb=0111

    In the second…

    • Answered
    • over 5 years ago
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  • hi. i wonder AMBA 3.0 AXI difference of data interleaving and write data interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.



    as you can see the first picture, slave send the read…

    • Answered
    • over 5 years ago
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  • hi. amba 3.0 axi interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.


    i wonder about interleaving and out-of order.

    AXI supports…

    • over 5 years ago
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  • hi. i wonder AMBA 3.0 AXI out-of order - WID & RID

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.

    Firstly, i very wonder AWID, WID and BID when write transaction…

    • Answered
    • over 5 years ago
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  • hi. i wonder AMBA 3.0 AXI handshake

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

       

    firstly, i very wonder the handshake…

    • Answered
    • over 5 years ago
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  • AXI4: Wider transactions than BUS width allowed?

    Robert Schilling
    Robert Schilling

    Hi AXI-experts,

    Does AX4 support burst sizes larger than the bus width?

    Narrow transactions are allowed, but do wider transactions also work?

    Best regards,

    Robert

    • over 5 years ago
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  • Questions on AXI4

    Naveen
    Naveen

    I have bunch of questions related to AXI. Can someone help me by answering those?

    AxSize can be varied across multiple transactions?

    whose duty is to set byte strobe in a transfer? Is it the master which should generate byte strobes along with un-aligned…

    • Answered
    • over 5 years ago
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  • Reason for having decouple write address, data channels in AXI4

    Naveen
    Naveen

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

    • Answered
    • over 5 years ago
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  • Question for AXI responce when access error

    Jun Usami
    Jun Usami

    HI,

    Does anyone know the minimum number of error responce (wready & rvalid) when AxLEN = 15?

    Does it need to respond 16th? or we can respond 1 only?

    Regards,

    -GARO

    • Answered
    • over 5 years ago
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  • Difference between FIXED and INCR burst in AXI?

    jayesh
    jayesh

    For any burst transfer Master has to pass only first address, for the consecutive transfer address calculation is taken care by Slave. So i want to know what is the basic difference in FIXED and INCR burst transfer?

    • Answered
    • over 5 years ago
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  • About AXI4 address channel and data channel handshake sequence

    田永丰
    田永丰

    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

    For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

    Remark:

    Just now, I noticed that…

    • Answered
    • over 6 years ago
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  • Significance of the WVALID signal in AXI

    Ronnie Dominic Joseph
    Ronnie Dominic Joseph

    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?

    • Answered
    • over 6 years ago
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