• Synopsys supports launch of Arm AMBA 5 AXI5, ACE5 protocols with 1st source code test suite and VIP

    Phil Dworsky
    Phil Dworsky

    Through a blog post by Jeff Defilippi, Arm has just announced the new Arm AMBA 5 AXI5, ACE5 and ACE5-Lite protocols; you can request the the latest AMBA 5 specs through a link in that blog. These protocols are employed by Arm's latest technology, including…

    • https://news.synopsys.com/2018-01-31-Synopsys-Announces-Verification-IP-and-Test-Suite-for-Arm-AMBA-ACE5-and-AXI5
    • View
    • Hide
    • over 2 years ago
    • Processors
    • Processors blog
  • Introducing the next generation of AXI and ACE protocols

    Jeff Defilippi
    Jeff Defilippi

    Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols have been implemented in Arm’s latest technology…

    • over 2 years ago
    • Processors
    • Processors blog
  • Arm Technical Training – Any time, any place

    Matt_Rushton
    Matt_Rushton

    Partner Training at Arm has been a great success over the last 15 years. It has expanded the knowledge and capabilities of our Partners’ Engineering teams by delivering classroom sessions to over 4000 attendees in 2016 alone and has helped our Partners…

    • over 2 years ago
    • Processors
    • Processors blog
  • Cycle-accurate Performance Analysis now available for latest AMBA5

    Nick
    Nick

    I already shared last month some details of work we have been doing with Arm on an HPC testchip, the good news continues with our announcement of extended support for the AMBA 5 protocol family with support for CHI.b in our Cycle-accurate performance…

    • over 3 years ago
    • Processors
    • Processors blog
  • AMBA

    VT
    VT

    Hello....!!!

    Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA AHB

    VT
    VT

    Hi ,

    In AHB specs, There is one note as below.

    Note

    Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation of the latency of accessing the bus. It is recommended…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA AHB SLAVE MULTIPLE SPLIT RESPONSES TO SINGLE MASTER

    Vishal
    Vishal

    Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI Locked Write and Lock Scope

    Deepak Ameta
    Deepak Ameta

    Hi All,

           1)  1st master is doing locked write transfer to 'X location after that, Can 2nd master initiate a read normal transfer for 'Y address in same slave? . And still unlocked transfer is not initiated by the 1st master?.…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACE - ReadNoSnoop transaction

    parita
    parita

    In ACE Specifications - ARM IHI 0022E, in ReadNoSnoop transactions how is the following other state of cacheline

    given on page number C4-197 transaction permitted :

    Start State  - ShareClean

    RRESP[3] - 0, RRESP[2] - 0

    End State - Invalid or UniqueCl…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    sourav
    sourav

    AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    Kun.Niu
    Kun.Niu

    AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

    As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?

    Kun.Niu
    Kun.Niu

    In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA3 AXI - Exclusive access

    Cao Phi Ho
    Cao Phi Ho

    1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location??

    Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID (first is 00 and second is 01) to the sam an address…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA3 AXI Relationship Between Channels

    Cao Phi Ho
    Cao Phi Ho

    In the document AMBA3 AXI (3.2 Relationships between the channels)

         Two relationships that must be maintained are:

              • read data must always follow the address to which the data relates…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • PLEASE HELP ME (AMBA3 AXI)

    Cao Phi Ho
    Cao Phi Ho

    1/ WHY "the width of the ID field at a slave interface is wider than the ID field at a master

    interface"??? Can you please explain in more detail the reason???

    2/ Do AXI protocol have support "read interleaving"???

    Thanks you so much…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AMBA AHB TRANSFER CONTINUE AFTER ERROR RESPONSE

    Vishal
    Vishal

    Hello everyone,


    Please describe me the transfer continuation process after ERROR response from the slave.ERROR response.jpg

    As shown in the above figure at cycle T4 if MASTER identifies the ERROR response from the SLAVE. Now, if the MASTER wants to continue the current transfer…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Please help about AMBA AXI 3.0

    Kiêm Nhật Minh
    Kiêm Nhật Minh

    I am a junior ASIC engineer. At the moment, I have three the question about AMBA AXI 3.0

    1. No combination paths between master and slave, all timing path must be registered. Why the VALID and READY signals can assert in the same time ?

    2. In the FIXED…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder AMBA 3.0 AXI difference of data interleaving and write data interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.



    as you can see the first picture, slave send the read…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. amba 3.0 axi interleaving

    In-Gyu.Lee
    In-Gyu.Lee

    I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading.


    i wonder about interleaving and out-of order.

    AXI supports…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder AMBA 3.0 AXI out-of order - WID & RID

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    Recently, I read "AMBA AXI Protocol.pdf". but i have two questions about AXI after reading.

    Firstly, i very wonder AWID, WID and BID when write transaction…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • hi. i wonder AMBA 3.0 AXI handshake

    In-Gyu.Lee
    In-Gyu.Lee

    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

    recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

       

    firstly, i very wonder the handshake…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI4: Unaligned read transactions

    Martin Trummer
    Martin Trummer

    Hi guys,

    I'm new to the AXI ecosystem.

    However, I have one question related to unaligned read transfers.


    Does AXI4 support unaligned read transfers although er are no strobe lines?

    If so, which data on the bus is written?

    To make it easier, discuss it…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Reason for having decouple write address, data channels in AXI4

    Naveen
    Naveen

    Can someone explain me the advantage of having decouple write address, data channels in AXI4?

    In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Question for AXI responce when access error

    Jun Usami
    Jun Usami

    HI,

    Does anyone know the minimum number of error responce (wready & rvalid) when AxLEN = 15?

    Does it need to respond 16th? or we can respond 1 only?

    Regards,

    -GARO

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Bare Metal Input/Output - Documentation?

    Mike Clark
    Mike Clark

    Does anyone know of an Idiot's Guide to this topic? In particular, how does a processor with no special I/O instructions issue a request, e.g. to a serial output device to output "Hello, World"? And how does Memory-Mapped I/O work in detail? Where is…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • View related content from anywhere
  • More
  • Cancel
<>