Arm offers Cycle Models for SystemC simulation. These models can be downloaded from Arm IP Exchange or created by users with Arm Cycle Model Studio (CMS). The models can be run in a SystemC only simulation environment from Accellera or in simulators from…

By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence

This is Part 3 of a 4 part series. Links below

Part 4

Cadence Interconnect Workbench

We have seen how a systematic process can be applied to validating…

By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence

This is Part 3 of a 4 part series. Links below

Part 3

Use-case Performance Analysis

In the previous two parts we introduced the challenges facing designers…

By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence

This is Part 2 of a 4 part series. Links below

Part 2

Performance Characterization

Because of the complexity of assembling and configuring the multitude…

By William Orme, Strategic Marketing Manager, Arm and Nick Heaton, Distinguished Engineer, Cadence

This is Part 1 of a 4 part series. Links below

Part 1

Introduction

The evolution of today’s system-on-chip (SoC) devices from uni-processor systems to heterogeneous…

Gone are the days when you used to use manual navigation aids to move around the town. Opening the Global Positioning System (GPS) to public use enticed technology firms to provide automation in navigation. Just by using your local coordinates and destination…

Earlier this month you may have noticed some press coverage regarding a collaboration between Xilinx, Arm, Cadence and TSMC to deliver 7nm test chip. 

There are some significant challenges assembling server SoCs for the infrastructure market with the latest…

In my last blog (Navigating SoC Verification with Perspec Portable Stimulus) I introduced the Accellera Portable Stimulus Standard (PSS) and how Cadence Perspec System Verifier supports the creation of portable baremetal Arm SoC integration tests using…

The modern SoC typically consists of billions of transistors and is normally designed with many modular IP blocks. Each of these blocks have been commercially licensed, developed or reused from previous designs. Integrating these components can be time…

Recently, Cadence Design Systems announced a suite of CCIX IP products which includes Controller, PHY and Verification IP. CCIX (pronounced “C6”) is an open coherent multichip standard that allows processors based on different instruction set architectures…