• Arm DynamIQ Shared Unit

    Errno
    Errno

    Hi,

    I read in the documentation for the Arm DSU that it provides a way-based partitioning of the shared L3 cache. What didn't get clear to me is if a core can still read/write from/to cache ways when they are assigned as private to another core.
    Is…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum