• how to understand L1 cache but L2 & L3 non-cached

    phil9980
    phil9980

    A5.6.6 Memory Behavior
    The Cortex-A55 core supports all the ARMv8 memory types.
    However, the following behaviors are simplified and so for best performance their use is not recommended:
    Write-Through

    Memory that is marked as Write-Through cannot be cached…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum