• Where can I find the docments about how the ARM cortex-A series pipeline works?

    Kun.Niu
    Kun.Niu

    Where can I find the docments about how the ARM cortex-A series pipeline works?

    Such as the first step of the pipeline do what and the second step of the pipeline do what, and also the Cortex-A series has different pipelines(such as cortex-A7 is different…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 structure can support max to 4 cores, I want ask the 4 cores have 4 part copy of the registers(37 registers * 4)?

    Kun.Niu
    Kun.Niu

    Cortex-A7 structure can support max to 4 cores, I want ask the 4 cores have 4 part copy of the registers(37 registers * 4)?

    In other words, each core have the same 37 registers or the 4 cores share the 37 registers?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A series's pipeline is for only one core or for all cores?

    Kun.Niu
    Kun.Niu

    For example, in ARM's related docments says that cortex-A7 support max to 4 cores and cortex-A8 support only one core, and the same time cortex-A7's pipeline is not the same with cortex-A8's pipeline. I want ask the cortex-A7's pipeline is for all the…

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    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?

    Kun.Niu
    Kun.Niu

    What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?

    In ARM's white paper(about the cortex-A7 and cortex-A15) says as follow:

    I want ask the in-order and out-of-order mean what?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • In ARM7 and ARM9 PC=current + 8, but in the cortex-A7(8-stage pipeline) the PC is also the same value(PC=current +8), how does this work?

    Kun.Niu
    Kun.Niu

    In ARM7 and ARM9 PC=current + 8, but in the cortex-A7(8-stage pipeline) the PC is also the same value(PC=current +8), how does this work?

    I think the cortex-A7 has 8-stage pipeline, the PC value is also current+8(this is back-forward for old design), but…

    • Answered
    • over 5 years ago
    • Processors
    • Classic processors forum
  • Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

    Kun.Niu
    Kun.Niu

    Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

    My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries are the same.

    ca7pipeline.PNGca15pipeline.PNG
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 contains MMU I want ask the MMU is contained in which part of the diagram?

    Kun.Niu
    Kun.Niu

    Cortex-A7 contains MMU I want ask the MMU is contained in which part of the diagram?

    Because in the CA7 block diagram doen't have a MMU part, so I think it is contained in which part.

    CA7_diagram.PNG
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Coprocessor instruction differencies?

    Juha Aaltonen
    Juha Aaltonen

    Are there differences between coprocessor instructions and instruction2:s?

    I mean:

    MCRR vs. MCRR2

    MRRC vs. MRRC2

    MCR vs. MCR2

    MRC vs. MRC2

    LDC vs. LDC2

    STC vs STC2

    I didn't find any differences in the encoding except the condition code, and no differences in…

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    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • NEON: Cortex A7 is 4 times slower than Cortex A8 ?

    Laurent
    Laurent

    I'm seeing Cortex-A7 cycle-timing table here :

    http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/


    For example, 

    VADD.F32 Dd, Dn, Dm takes 2 cycles

    VADD.F32 Qd, Qn, Qm takes 4 cycles

    same goes for VMUL..

    Is this really the case…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Register 'names' in instruction descriptions

    Juha Aaltonen
    Juha Aaltonen

    The registers in the instructions are usually 'named' Rn, Rm, Rd, ...

    Is there some deeper meaning in the names?

    Usually Rd seems to mean 'destination register'

    Sometimes Rn is the only operand, sometimes it's Rm. Also the place in the instruction…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • UNPREDICTABLE in instruction description (Lord! yet another question)

    Juha Aaltonen
    Juha Aaltonen

    In quite many instruction descriptions it says:

    if d == 15 then UNPREDICTABLE;

    What does this mean?

    Can the instruction really work in some unexpected way in each such case or what?

    I guess if I use a bit-reversing instruction on PC I should expect that…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What's the single cycle Load-Use in ALU mean?(In Cortex-A7)

    Kun.Niu
    Kun.Niu

    What's the single cycle Load-Use in ALU mean?

    This is in the follow picture:

    CA7_detailpipeline.jpg
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Pseudocode for saturation (Oh no, not again)

    Juha Aaltonen
    Juha Aaltonen

    In some instruction descriptions there are calls to SignedSatQ (directly or indirectly).

    The pseudocode for SignedSatQ:

    (bits(N), boolean) SignedSatQ(integer i, integer N)

    if i > 2^(N-1) - 1 then

    result = 2^(N-1) - 1; saturated = TRUE;

    elsif i < -(2…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?

    Kun.Niu
    Kun.Niu

    The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?

    I find some answers say that dual-issue means that the cortex-A7 can issue two instructions per clock.

    But in the cortex-A7's pipeline diagraph, it has integer…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How does the BTIC(branch target instruction cache) works?

    Kun.Niu
    Kun.Niu

    in cortex-A series, most core has the BITC(branch target instruction cache). It is contained in the prefetch unit.

    Branch Target Instruction Cache

    The PFU also contains a four-entry deep Branch Target Instruction Cache

    (BTIC). Each entry stores up to two…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SMMU initialization

    Dav
    Dav

    Hi,

    Where i can find step-by-step instruction how to init SMMU PA->IPA translation? (With procedure description)

    (i checked ARM ® System Memory Management document, but i was not found exact instruction how to setup correct translation).

    I have ARM…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ASR #32

    Juha Aaltonen
    Juha Aaltonen

    In the SSAT instruction description it says:

    ASR #32 Arithmetic right shift by 32 bits, permitted only for encoding A1.

    Encoded as sh = 1, immsh = 0b00000.

    What does that mean?

    Isn't ASR #32 the same as ASR #31?

    I understand that it shifts (with "sign…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The madman strikes again - ADD/SUB SP

    Juha Aaltonen
    Juha Aaltonen

    Is there something special in the instructions ADD (SP plus register, ARM) and SUB (SP minus register)?

    I didn't find anything different from the basic ADD  (register) and SUB (register) except the documentation:

    <Rd> The destination register…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is First-level table skippable? (VMSA)

    Jongseok Kim
    Jongseok Kim

    Hi forks. I am a newbie engineer for arm-processor and I have a question about VMSAv7-32.

    According to ARMv8 architecture manual, page 3592: arm processor can skip first level table if a first level table would contain only one entry..

    How arm processor…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Funny asymmetry with banked register names

    Juha Aaltonen
    Juha Aaltonen

    Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but

    one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.

    In document (ARMv7-A/R ARM Issue…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • LDRT and rrx'd operand

    Juha Aaltonen
    Juha Aaltonen

    I was wondering about LDRT when the operand is rrx'd. Which where does the carry-bit come from?

    LDRT{<c>}{<q>} <Rt>, [<Rn>], +/-<Rm> {, <shift>}

    RRX Rotate right one bit, with extend. Bit[0] is written to shifter_carry_out…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to learn ARM

    Amey Chaware
    Amey Chaware

    Hi everyone!!

    I am looking to work on some projects using ARM. I have completed a basic course on ARM M3/M4 (UT Austin 6.01x by Jon Valvano and Ramesh Yerraballi) online. Now, I want to learn advanced things, especially real-time applications. How should…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to compare ACPI states (Sx, Cx) with ARM Cortex-A processor states (Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop, Deep Sleep) ?

    Kratzer
    Kratzer

    Hello,

    I'm a student and I'm interested in how to compare ACPI Sleep States (Sx) and processor power states (Cx) with ARM Cortex-A states e.g. Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop, Deep Sleep

    Thank you

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 Processor DSP

    Акоб
    Акоб

    Hello everyone.

    I am new usage of Allwinner A20.

    I read in Cortex-A7 specification, that it have DSP & SIMD extensions.

    And if there are digital processing unit in processor, can i use it? Can i drop on it some code, as any other DSP? And if yes, will…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Sampling/tracing memory addresses

    chansen3
    chansen3

    Is there any ARM tool that will sample or trace addresses of memory accesses for a processes?  And specifically for a Cortex A72-A.  It appears that there is support for this with the Statistical Profiling Extension or an Embedded Trace Macrocell, but the…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
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