Hi all,

I am  a master student in germany and doing my thesis currently. I wanted to measure CPU cycles using emulation/simulation for some code that is running on a cortex m4F processor based board. I had QEMU in mind at initial but it turns out it doesn…

This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

Hi.

I'd like to get the simulation waveform dump file when I do run the simulation of AT421-MN-80001.

there is some options in makefile such as 

# NC verilog option
NCSIM_OPTIONS = -unbuffered -status -LICQUEUE -f ncsim.args -cdslib cds.lib -hdlvar…

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

I am working on a GPIO IP for Designstart Pro Cortex-M0. Now in my Simulation there are some Read-Modify-Write cycles in order to set only single bits in a 32 bit register.

If the GPIO register is 0x0000000X and I just want to set bit 16, GCC produces…

Hi,

     I am using Cortex-M0 DesignStart Pro. When I simulation intrrupt_demo test case, I found that IRQ[31:0]  always 0, Is this correct?

     I saw the document , the interrupt_demo is Demonstration of interrupt features, but if no interrupt signal input…

Deare

       I am using Cortex-M0 DesignStart Pro. When I use my program to simulation, I found the HADDR from 0, to 4, and the to ffff_fffd8, the  HRDATA is  0x2000_06f8 and 0x800_0159，the HADDR should not be ffff_ffd8，So I think it's unusual, but I don't know…

I saw, and tried in the past already, to simulate the Cortex-M0. It does not really matter efficiency, customization and so on, but only the learning process behind a steup for a correct very basic simulation.

I was trying to setup a Linux machine, when…

We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside),  we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "…

I am a beginner, trying to run the "hello" testcode on the M0 but when I run the simulation, I am getting the following signals which don't seem to give the relevant UART output for "Hello world".

Hi,

I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…

Hi.

TESTNAME=bootloader test sequence is in  BP210 CM3 test sequence,

In especially, we could find the below code,

then we got the below error message when we ran the simulation.

23490 ns UART: CMSDK Boot Loader 
27270 ns UART: - load flash 
45710…