Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…