Hi.
I'd like to get the simulation waveform dump file when I do run the simulation of AT421-MN-80001.
there is some options in makefile such as
# NC verilog option
NCSIM_OPTIONS = -unbuffered -status -LICQUEUE -f ncsim.args -cdslib cds.lib -hdlvar…
Hi.
I'd like to get the simulation waveform dump file when I do run the simulation of AT421-MN-80001.
there is some options in makefile such as
# NC verilog option
NCSIM_OPTIONS = -unbuffered -status -LICQUEUE -f ncsim.args -cdslib cds.lib -hdlvar…
Deare
I am using Cortex-M0 DesignStart Pro. When I use my program to simulation, I found the HADDR from 0, to 4, and the to ffff_fffd8, the HRDATA is 0x2000_06f8 and 0x800_0159,the HADDR should not be ffff_ffd8,So I think it's unusual, but I don't know…
We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside), we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "…