• Whitepaper: Understanding Write Combining on Arm

    Charlotte Christopherson
    Charlotte Christopherson
    Author: Pavel Shamis, Principal Research Engineer

    Write CombiningWrite Combining (WC) is a specialized memory type defined by the x86-64 architecture that is used for gathering multiple stores into burst transactions over the system bus. WC is commonly used on x86-64…

    • Understanding_Write_Combining_on_Arm_V.1.0.pdf
    • 3 months ago
    • Arm Research
    • Resources
  • Why the address of fuction printed is not same as the one mentioned in map file

    Gopu
    Gopu

    In Cortex-M7,Why the address of fuction printed is not same as the one mentioned in map file.

    i.e, My function address is 0x00473dbc in map fle, but it is diffrent, if we print it in my program.

        

    • 3 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Memory profiling (ARM Musca A1 Board)

    Lica
    Lica

    Hey !

    So, I am trying to know how much bandwidth each memory of my system has. From what I have searched, the STREAM benchmark is the most recommended. The only problem is that I am using a resource-limited board (ARM Musca A1), so automatically it is…

    • 7 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Programming BRAM with JTAG--Help regarding knowledge source requested.

    Mezan1
    Mezan1

    Hi 

    I am trying to program a BlockRAM inside FPGA using JTAG on spartan 6. I am using core generator provided by Xilinx. Is it possible? Is there any document that I can go through to know how to interface a parallel flash with JTAG? My intention is to…

    • Answered
    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • How does RTOS use MPU on Cortex-M?

    Himal Subedi
    Himal Subedi

    1. What is more suitable for running RTOS: Cortex-A or Cortex-R or Cortex-M? 

    2. I want to make my own RTOS on Cortex-M: How to use MPU for protecting tasks? 

    • 8 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • MPAM support in FVP

    Matteo Zini
    Matteo Zini

    Hello,

    I'm a student and I'm about to begin the development of a software module to support MPAM on an ARM system.

    I was willing to test the software on an fvp platform, but I'm not able to find any reference about the memory address of the MPAM…

    • 9 months ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Migrating from armcc to armclang causes section type conflict

    embedded.kyle
    embedded.kyle

    I am trying to migrate an existing project from armcc to armclang using Keil. Most of the new errors generated by simply switching the compiler have been easily cleaned up with help from their migration guides. But I cannot seem to fix the following error…

    • over 1 year ago
    • Software Tools
    • Arm Compilers forum
  • Emerging Standalone NVM – Moving Beyond the Hype

    Wendy Elsasser
    Wendy Elsasser

    Numerous articles and papers have been written on emerging non-volatile memory (NVM) over the last few decades. These emerging technologies have been hyped as either: 

    1. A DRAM replacement in the optimistic case
    2. A Flash replacement
    3. A new memory tier between DRAM…
    • over 1 year ago
    • Arm Research
    • Research Articles
  • How does the NEON access Memory?

    bearfish
    bearfish
    Note: This was originally posted on 5th May 2008 at http://forums.arm.com

    I have a question about how to get the maximum calculation capability of NEON. In our video processing application, we should access several frame video. Then if the video is HD…
    • over 7 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Setting up TCM Memory in ARM926EJ-S

    bekiricli bekiricli
    bekiricli bekiricli
    Note: This was originally posted on 20th October 2008 at http://forums.arm.com

    Hi all,

    I am currently trying to turn on TCM in ARM926EJ-S where there is 64K for ITCM, DTCM and internal SRAM.
    I have decided to use it as:
    32K ITCM
    16K DTCM
    16K SRAM

    Therefore…
    • over 7 years ago
    • Processors
    • Classic processors forum
  • Problem: SRAM region is full

    civil777
    civil777
    Note: This was originally posted on 12th December 2008 at http://forums.arm.com

    Hello!

    I am getting the compiler error that "sram region is full", and I am trying to identify the possible causes. I know this is basic problem, but I am a newbie!…
    • Answered
    • over 7 years ago
    • Processors
    • Classic processors forum
  • How to force ARM core into debug state when DBGEN was tied LOW?

    Shih-Yen Kao
    Shih-Yen Kao
    Note: This was originally posted on 11th January 2009 at http://forums.arm.com

    [size=3][font="Courier New"]
    Hello,

        After our SoC(ARM926EJ-S inside) was mounted on our development board, ARM Multi-ICE was able to connect to it and get its processor…
    • Answered
    • over 7 years ago
    • Processors
    • Classic processors forum
  • TCM and ARM1136

    hongkongrr hongkongrr
    hongkongrr hongkongrr
    Note: This was originally posted on 13th January 2009 at http://forums.arm.com

    Hi,

    I am trying to use DTCM to see if I can improve performance of my program on ARM1136.

    I wrote a test program that just read/write TCM and read/write to RAM.  However anlayzing…
    • Answered
    • over 7 years ago
    • Processors
    • Classic processors forum
  • Dynamic loading ARM9 executables.

    veesh852 veesh852
    veesh852 veesh852
    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    Hi all,

    Our system have one DSP and one ARM and system will boot with DSP  then DSP  should load ARM executable in ARM program memory.  how to do this ?.
    We tried…
    • Answered
    • over 7 years ago
    • Processors
    • Classic processors forum
  • ARM Cortex ICode, DCode, System buses

    Felix Varghese
    Felix Varghese
    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
    …
    • over 7 years ago
    • System
    • SoC Design forum
  • Shortest code for memory to memory transfer

    subin t
    subin t
    Note: This was originally posted on 16th March 2009 at http://forums.arm.com

    Hi All,
        Can anyone tell me what is the shortest code I can use for cortex M3 to transfer (a few words) from one memory location to other(without using the DMA).  It should…
    • over 7 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • where is the syntax for .sct (scatter file content) defined?  Did ARM originate this file type?

    Piero Generale
    Piero Generale

    Automatically generated when I create a new project with Keil:

    my.sct

    LR_IROM1 0x00400000 0x00020000  {    ; load region size_region

      ER_IROM1 0x00400000 0x00020000  {  ; load address = execution address

       *.o (RESET,…

    • Answered
    • over 5 years ago
    • Software Tools
    • Keil forum
  • how i can store/erase C variable in the internal non volatile memory of lpc2148?

    Durlabhsoni
    Durlabhsoni

    I m already read its datasheet but i unable to do this ......please help me to understand.

    • over 4 years ago
    • Software Tools
    • Keil forum
  • what is the difference between the device memory and the strongly-order memory ?

    Dong Luo
    Dong Luo
    Note: This was originally posted on 21st June 2011 at http://forums.arm.com

    Dear All,

           Both device and strongly-order memory are used to model memory-mapped peripherals and I/O locations in ARMv7 architecture.  And the architecture specification says…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory partitioning on Cortex-A7

    Man-Ki Yoon
    Man-Ki Yoon

    Hello,

    I am using a quad-core Cortex-A7 (on Raspberry PI 2). I run a Linux on Core 0,1,2 and a baremetal application on Core 3. My goal is to protect the baremetal application from the rest (i.e., the linux side). Initially I thought that I can do this…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data

    Sid
    Sid

    Hi there,

    good morning.

    I am using TMC as Embedded Trace Fifo and testing it for FULL condition.

    Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF?

    So that eventually it gets full setting the FULL bit in STS…

    • DDI0461B_tmc_r0p1_trm(1).pdf
    • over 4 years ago
    • System
    • SoC Design forum
  • Low-Level NOR Chip Interfacing and Embedded File System (EFS) Resources

    japolo
    japolo

    Hello all, 

    I am currently working on a project that requires me to interface with a single external NOR flash chip from Cypress (S29GL064880TFV030), the microcontroller that I'm working with is a STM32F407ZGT7 (LFQP144 Pin Package). I've read through…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • how to use the 16MB SDRAM on keil MCB 1800?

    Shreyas007
    Shreyas007

    I wanted to use the 16MB SDRAM on the keil mcb 1800 board.

    I didn´t find any examples on how to do it?

    Do I have to make any physical connections to use it? 

    It would be great if someone can provide the steps for it.

    Thanks

    • over 1 year ago
    • Software Tools
    • Keil forum
  • Cortex-M3 Hard Fault - find cause?!?!?!?

    Tim Borland
    Tim Borland

    Hello all,

    I'm new to the ARM platform and I'm having a problem discovering why my code is generating a Hard Fault.

    My hardware is an mbed platform board with the NXP LPC1768 processor.

    The code in question works when compiled using the mbed…

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARM Cortex-A9 | Non-cacheable memory range

    S R Chidrupaya
    S R Chidrupaya
    Note: This was originally posted on 23rd May 2013 at http://forums.arm.com

    Hi all,


    I am designing an application on  xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using one of the arm cores two run a part of the application…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
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