• Test Errors with DesignEval Kit

    DarshanSatya
    DarshanSatya

    I am currently in Evaluation phase of ARM Design Kits.

    I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide to compile the RTL and run the tests.

    But, unfortunately after compiling the RTL I am getting a stack…

    • Answered
    • over 2 years ago
    • DesignStart
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  • Test Errors with DesignEval Kit (arm_cortex_m3_designstart_eval_rtl)

    DarshanSatya
    DarshanSatya

    I am currently in Evaluation phase of ARM Design Kits.

    I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide_100895_0000_00_en.pdf

    to compile the RTL and run the tests.

    But, unfortunately after compiling the…

    • Answered
    • over 2 years ago
    • DesignStart
    • DesignStart forum
  • DesignStart Eval on Terasic DE10-Standard Board

    ag4inst4ll0dds
    ag4inst4ll0dds

    Hello,

    For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
    The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

    If I try to compile the ".sof" file of the Eval package in Quartus Prime…

    • Answered
    • over 2 years ago
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  • how to implement mbed_blinky example on mps+2 board ?

    zhenyuliu
    zhenyuliu

    hi, GUys

       i buy a mps+2 board  and try to implement  mbed_blinky examples. but i meet issues on debugger and download axf files.

         now i can:

            1. export mbed_blinky examples for keil 

            2. compile success and generate axf file

            3. download fail

    …
    • Answered
    • over 2 years ago
    • DesignStart
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  • First compile, verilog files missing

    LeChuck
    LeChuck

    Hi,

    I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

    So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

    • Answered
    • over 2 years ago
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  • ARM CortexM3 Designstart on the fpga can't run the compiled c code itself

    chinaboy
    chinaboy

    Dear all

    I encounter a confusion that  I compile a piece a c code and generate HEX file( as instruction rom's initialization file) which is download to the fpga whit the cortex m3 prototype of Verilog code .but the M3 system can't run itself .when I…

    • Answered
    • over 2 years ago
    • DesignStart
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  • Cortex-M0 example system

    pangda
    pangda

    Hi,

    II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

    D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

    • Answered
    • over 2 years ago
    • DesignStart
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  • Different Address of Reset Handler!

    jayce
    jayce

    Hi there,

    Why the address of reset handler is different from waveform and assembly code for hello testcase?

    This is obtained after compiling hello.c using Keil uVision 5.

    Reset_Handler
    0x000001c0: 4809 .H LDR r0,[pc,#36] ; [0x1e8] = 0x2a1
    0x000001c2:…

    • over 2 years ago
    • DesignStart
    • DesignStart forum
  • Modelsim for CM3 path error

    urian
    urian

    Hi,

    I want to simulate CM3 Designstart with Modelsim.

    When I launch Modelsim from Quartus 17.2 most of the files compile. But I get the following error:

    ** Error: C:/projects/AT421-MN-80001-r0p0-02rel0/smm/logical/smm_common_fpga/verilog/fpga_pll_speed…

    • Answered
    • over 1 year ago
    • DesignStart
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