• 在4 Core的ARM Cortex-A9系统中如何测量一个内核对共享内存访问的开销?最大开销是多少?最小开销等如何测量?

    BeDook
    BeDook

    如题,在四核的Arm Cortex-A9中如何测量Core对共享内存访问的开销?最大和最小开销是多少?这里开销具体是指什么?

    需要考虑L1 L2 Cache么?最大开销是不是访问主存(不经过Cache)?最小开销是不是从L1 Cache读写?这里需不需要考虑数据量大小?比如对某块内存memset()写一定大小的数据 几K的。。。其最大和最小开销如何测量?

    • over 1 year ago
    • 中文社区
    • 中文社区论区
  • Disable data prefetching in a Cortex-A53 running Android

    DNovo
    DNovo

    Dear Experts,

    I would like to disable the data prefetching engines of the L1 and L2 caches on a MediaTek-X20 board which includes a quad Cortex-A53 cluster and runs Android.

    I have tried to include in the Linux kernel code (at kernel/init/main.c) a call…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to understand L1 cache but L2 & L3 non-cached

    phil9980
    phil9980

    A5.6.6 Memory Behavior
    The Cortex-A55 core supports all the ARMv8 memory types.
    However, the following behaviors are simplified and so for best performance their use is not recommended:
    Write-Through

    Memory that is marked as Write-Through cannot be cached…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareable domain and cache policy problem

    zhi
    zhi

    Hi,

    I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • L2 Cache(Pl310) initialisation sequence

    Shravan Alugala
    Shravan Alugala

    Hi ,

    I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.

    Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Disabling L2 cache for CPU1 (Zynq-7000)

    irie
    irie

    Hello people,

    we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one handles DMA configurations and its interrupts. We have…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Using shareable attribute in MPU configuration of Cortex R4

    Ilan
    Ilan

    Good day all,

    I'm working with a SOC with dual Cortex-R4 that comes with MPU.

    Due to the SRAM limitation and other restrictions, I'm not using any embedded linux or any other SMP RTOS.

    Currently I'm working on the optimization of the flow, so I'm…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • PL310 counters in Samsung Exynos 4 Quad using Streamline

    Marcelo Salazar
    Marcelo Salazar

    Question

    L2 cache misses in Samsung Exynos 4 Quad using Streamline

    Is it possible to measure PL310 events using the DS-5 Streamline? The target device is Samsung Galaxy S3 with Exynos 4 Quad SoC and Cortex A9 cores. The device runs Android.

    -Dhinaka…

    • over 6 years ago
    • Software Tools
    • Arm Development Studio forum
  • L2 cache misses in Samsung Exynos 4 Quad using Streamline

    Dhinakaran Pandiyan
    Dhinakaran Pandiyan

    Is it possible to measure PL310 events using the DS-5 Streamline? The target device is Samsung Galaxy S3 with Exynos 4 Quad SoC and Cortex A9 cores. The device runs Android.

    -Dhinakaran

    • Answered
    • over 6 years ago
    • Software Tools
    • Arm Development Studio forum