• 在4 Core的ARM Cortex-A9系统中如何测量一个内核对共享内存访问的开销?最大开销是多少?最小开销等如何测量?

    BeDook
    BeDook

    如题,在四核的Arm Cortex-A9中如何测量Core对共享内存访问的开销?最大和最小开销是多少?这里开销具体是指什么?

    需要考虑L1 L2 Cache么?最大开销是不是访问主存(不经过Cache)?最小开销是不是从L1 Cache读写?这里需不需要考虑数据量大小?比如对某块内存memset()写一定大小的数据 几K的。。。其最大和最小开销如何测量?

    • over 1 year ago
    • 中文社区
    • 中文社区论区
  • Disable data prefetching in a Cortex-A53 running Android

    DNovo
    DNovo

    Dear Experts,

    I would like to disable the data prefetching engines of the L1 and L2 caches on a MediaTek-X20 board which includes a quad Cortex-A53 cluster and runs Android.

    I have tried to include in the Linux kernel code (at kernel/init/main.c) a call…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to understand L1 cache but L2 & L3 non-cached

    phil9980
    phil9980

    A5.6.6 Memory Behavior
    The Cortex-A55 core supports all the ARMv8 memory types.
    However, the following behaviors are simplified and so for best performance their use is not recommended:
    Write-Through

    Memory that is marked as Write-Through cannot be cached…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareable domain and cache policy problem

    zhi
    zhi

    Hi,

    I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACE protocol : Eviction and snoop request at same time

    Chakri Myneni
    Chakri Myneni

    How to handle below scenario ?

    • At time t1 let us suppose L1 data cache is evicting a line and write address is sent on write address channel by asserting AWVALID (AWREADY is high)
    • At same time t1, there is a snoop request from interconnect on snoop address…
    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • L1 Cache Eviction Corrupting DDR on A9

    yottaflop
    yottaflop

    Hi All!

    I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU.

    I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table gets corrupted by what appears to be L1 evictions…

    • Answered
    • over 4 years ago
    • System
    • Embedded forum
  • Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM

    claudiu
    claudiu

    Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5?

    Thank you!

    [1] infocenter.arm.com/.../index.jsp

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why Cache L1 Counters disable on Streamline

    Olfat
    Olfat

    Hello every one,

    ARM DS-5 (University) streamline to read counter events from Beagle Bone Black board. for some reason i can not get the l1Caches counter to work. Any Advice?

    Untitled.png

    Thanks

    • Answered
    • over 5 years ago
    • Software Tools
    • Arm Development Studio forum
  • Using shareable attribute in MPU configuration of Cortex R4

    Ilan
    Ilan

    Good day all,

    I'm working with a SOC with dual Cortex-R4 that comes with MPU.

    Due to the SRAM limitation and other restrictions, I'm not using any embedded linux or any other SMP RTOS.

    Currently I'm working on the optimization of the flow, so I'm…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum