Hello 

I'm working on the Bootloader stage (EL2), I'm trying to enable Interrupts with gic v3 in that stage

I've enabled routing IRQ, FIQ and Aborts from EL0, EL1 and EL2 to EL2  using these piece of code 

MRS X0, HCR_EL2
AND X0, X0, 0xFFFFFF…

I wonder, is AFF1 in ICC_SGI1R_EL1 also a bit-mask or does it address directly the cluster?

So does AFF1 == 3 address cluster 3 or cluster 0 and cluster 1.

Hey Guys,

I'm trying to emulate FreeRTOS for Cortex-R52 and I was half way successful.

Everything is working except the Tick Interrupts.

Right now I can create and run tasks using Co-Operative Scheduling but I need Preemption to work.

I've configured…

Hello,

we have a board using Armada 3720 SOC, which contains two Cortex-A53s and one Cortex-M3 used as secure-coprocessor. The interrupt controller is GIC-500.

The M3 has access to all registers that A53 can see. The first A53 has RVBAR at 0xffff0000 where…

Hi,

In a GICv3 based system, is it possible to have the following configuration:

While running NS-EL1/EL0:

-NS Group1 interrupts triggered as IRQ to NS-EL1

-Secure Grp1 interrupts routed as FIQ to EL3

-Secure Grp0 interrupts routed as FIQ to EL3

This…

Hi all,

I am investigating the GIC Stream protocol and having a confusing issue as the title.

The figure below shows the case that an interrupt is retrieved from CPU interface.

As explained in the GIC Stream Specification, there may be 2 reasons:

1. The…

As stated in GIC v3 Arch: After powering up a PE, software must set ProcessorSleep to 0 and wait until ChildrenAsleep == 0.

Can you please also state the conditions for GICR_WAKER.ChildrenAsleep to go 0? As in my case at a particular operating frequenc…

I'm using a cortex-a53 FVP model. It comes only with GICv3, but by reading the ICC_SRE_EL3.SRE bit I see this implementation has legacy support.

Before leaving EL3 I configure all interrupts to group 1 in the distributor and set the PMR in the interfaces…