• fvp: configuring gicv3 for operation in el1ns

    a.surati
    a.surati

    I am trying to program FVP_Base_RevC-2xAEMv8A (el0, el1 and el3 implemented).

    The bare-metal program (@ cpu0) runs at el3, and configures the gic and the system counter registers as shown below:

    icc_sre_el3 = 0xf;
icc_ctlr_el3.pmhe = 1;
icc_ctlr_el3.eoimode_el1ns…

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum

  • ARMv8-M - toolchains / virtual platforms

    Pierre
    Pierre

    Hello,

    I would be interested to try the new features of the ARMv8-M architecture, in particular v8-M TrustZone, but I can't find necessary tools in order to do so.

    1. I need a toolchain that supports the new instructions introduced with v8-M (SG, BXNS…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum