Hi,

I'm trying to build the MPS2 FPGA project (unmodified, as it is supplied in the kit) and constantly getting an error message saying "Quartus Prime Software quit unexpectedly".

It always crashes at the "Partition Merge" stage after…

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

I want to simulate CM3 Designstart with Modelsim.

When I launch Modelsim from Quartus 17.2 most of the files compile. But I get the following error:

** Error: C:/projects/AT421-MN-80001-r0p0-02rel0/smm/logical/smm_common_fpga/verilog/fpga_pll_speed…