Hi,

I'm trying to build the MPS2 FPGA project (unmodified, as it is supplied in the kit) and constantly getting an error message saying "Quartus Prime Software quit unexpectedly".

It always crashes at the "Partition Merge" stage after…

Hi,

After compiling the MPS2+ FPGA designstart project (unmodified, as-is out of the box), i'm failing to run it on the FPGA.

While the already downloaded image that arrives on the FPGA runs fine (i run the demo application), the image I compiled…

Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

I tried to start with Linux to see if at least the "make" commands are working. Problem…

I am currently in Evaluation phase of ARM Design Kits.

I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide to compile the RTL and run the tests.

But, unfortunately after compiling the RTL I am getting a stack…

I am currently in Evaluation phase of ARM Design Kits.

I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide_100895_0000_00_en.pdf

to compile the RTL and run the tests.

But, unfortunately after compiling the…

Hello,

For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

If I try to compile the ".sof" file of the Eval package in Quartus Prime…

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Dear all

I encounter a confusion that  I compile a piece a c code and generate HEX file( as instruction rom's initialization file) which is download to the fpga whit the cortex m3 prototype of Verilog code .but the M3 system can't run itself .when I…

Hi,

I want to simulate CM3 Designstart with Modelsim.

When I launch Modelsim from Quartus 17.2 most of the files compile. But I get the following error:

** Error: C:/projects/AT421-MN-80001-r0p0-02rel0/smm/logical/smm_common_fpga/verilog/fpga_pll_speed…