Hi there,

I am the author of the open source Orbuculum tools for SWO data parsing on CORTEX-M targets. I am currently expanding those tools by implementing 1, 2 & 4-bit parallel TRACEDATA capture from CORTEX-M3/M4 CPUs using a small FPGA connected to…

We started working on a daughter card we want to connect via the expansion ports, and we trying to understand the 52 IOs of the two expansion ports frequency capabilities (Board aspect) , is there any information regarding it ?

Are there any schematics…

Hi,

I'm trying to build the MPS2 FPGA project (unmodified, as it is supplied in the kit) and constantly getting an error message saying "Quartus Prime Software quit unexpectedly".

It always crashes at the "Partition Merge" stage after…

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

Hi,

After compiling the MPS2+ FPGA designstart project (unmodified, as-is out of the box), i'm failing to run it on the FPGA.

While the already downloaded image that arrives on the FPGA runs fine (i run the demo application), the image I compiled…

This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

Hi.

I came across Cortex-M3 DesignStart Eval r0p0-02rel0 implementing to the boards name of  ALTERA's MPS2+ from here https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-system .

But I'm looking for Xilinx board…

Is it possible to directly program the FPGA in the MPS2+ board with the Altera Quartus Programmer?

As far as I understand is the MPS2+ 10 Pin FJTAG port not compatible to the Alter USB blaster.

Is there another way to do this? 

Hello,

I want to use an USB Blaster cable for rapid FPGA prototyping on the MPS2+. 

The cables differ very much in price.  Is it recommended to buy an original Altera for over 200 Euro or can I use a cheaper nonamee one?

Could you please recommend a cable…

Hi everyone,

I'm using Windows 10 operating system(i couldn't know if this is relevant to second part of my problem) and I want to embed Cortex M0 Designstart Design Kit on a Xilinx FPGA board. I'm currently trying to synthesize (AT510) r1p0-00rel0…

Hello expert:

In MSP2+ board, I found a micro USB connector and some ARM debugger connectors. Can I configure FPGA and run DS-5 using the same micro USB?

Thanks

Jimmy

Hi,

I am using Quartus Prime Lite 17.0.2 for building Cortex-M3 DesignStart RTL.

I can successfully build the RTL, but I got some critical warnings as follows. Can I ignore these warnings? Is there any effects on the design by these warnings?

Critical…

All,

I received the Versatile Express Cortex-M Prototyping System + and am using DesignStart. I powered on the board and the operating system booted up without any problems.

In the V2M_MPS2/MB/HBI0263C/board.txt file, the following are the sequence of…

Hello, I started to tinker with the most basic Cortex-M0 from the DesignStart.
I am using Modelsim Student Edition, which run only on Windows (or Linux through Wine).

I tried to start with Linux to see if at least the "make" commands are working. Problem…

I am currently in Evaluation phase of ARM Design Kits.

I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide to compile the RTL and run the tests.

But, unfortunately after compiling the RTL I am getting a stack…

I am currently in Evaluation phase of ARM Design Kits.

I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide_100895_0000_00_en.pdf

to compile the RTL and run the tests.

But, unfortunately after compiling the…

Hello,

For my bachelor thesis I have to implement the RTL-Code of the Cortex-M3 in the DE-10 Standard Board.
The FPGA on the Terasic DE-10 Standard is the Cyclone V  5CSXFC6D6F31C6.

If I try to compile the ".sof" file of the Eval package in Quartus Prime…

Hello,

I try to implement the Cortex-M3 processor on an FPGA via Quartus Prime. I set up the SSE050 Subsystem and tried to connect several peripherals to the board. I want to test the functionality with a uVision project lighting some LEDs. To have access…

I download arm cortex m3 prototype  to the CYCLON 5 FPGA .Then use keil to debug the software but when click he debug button ,I encountered an error like the one shown above.

I don't know how to solve the problem 

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hello,

I'm trying to connect the DesignStart Eval System to the BME280 Environmental Sensor via SPI. I used the SPI Shield0 Pins (EXP[11 to 14]) to set the connection and activated alternate functions in uVision for these pins. But how can I set up the…