I am currently in Evaluation phase of ARM Design Kits.

I am using the exact steps present in arm_cortex_m3_designstart_eval_rtl_and_fpga_quick_start_guide_100895_0000_00_en.pdf

to compile the RTL and run the tests.

But, unfortunately after compiling the…

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …