Hello all,

I downloaded the Cortex-M1 DesignStart package for Xilinx FPGAs and followed the instructions given in the training videos. However, the HDL wrapper for the block diagram appears under "non-module files" in Vivado. Due to this I am not able…

Hi,

I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…

Hi, My name is Vedula. My back ground is 23 yrs in ASIC industry. Did Design/Verification/Validation. I want to get my hands dirty with DesignStart. I am interested in FPGA part. 

I Just downloaded Cortex-M1 DesignStart FPGA - Xilinx Pkg.

To start with…

Hello,

I have already played around with the Cortex-M1 reference designs for Xilinx Spartan and Artix boards, can you give an indication of what your maximum target frequency for the processor IP core is? Are the referenced 100 MHz a good design practice…

Hi.

I started to play with DesignStart FPGA and implemented example design to a Xilinx Arty board. I successfully imported BSP to Keil, did some changes there and generated a new bitstream. Now I would like to start debug session in Keil, but I don't have…

Hi all,

My main goal is to rebuild the core and the peripherals of an STM32F0xx into an FPGA. An idea to realize this is to use a softcore and build up the used peripherals by connecting them to the supported BUS system.

As far as I understand is the…