Hi everyone,

I'm using Windows 10 operating system(i couldn't know if this is relevant to second part of my problem) and I want to embed Cortex M0 Designstart Design Kit on a Xilinx FPGA board. I'm currently trying to synthesize (AT510) r1p0-00rel0…

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

Hi.

TESTNAME=bootloader test sequence is in  BP210 CM3 test sequence,

In especially, we could find the below code,

then we got the below error message when we ran the simulation.

23490 ns UART: CMSDK Boot Loader 
27270 ns UART: - load flash 
45710…

For the last weeks, I have been trying to get this new version to work. I did the same as with the previous version and now it is running on the Xilinx Nexys4. However, honestly I do not have any idea how to get the debugging to work. I defined the pins…

Wenkwei asked: "with the M3 designstart CMSDK, is it possible to design multi-master bus? In the IoT Cortex-M TRM, only an ahb-lite structure is illustrated. That document does mention AHB and APB expansion through INTEXP[1:0] but what if there are more…