Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.

And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using…

Hello all,

I downloaded the Cortex-M1 DesignStart package for Xilinx FPGAs and followed the instructions given in the training videos. However, the HDL wrapper for the block diagram appears under "non-module files" in Vivado. Due to this I am not able…

In our product, cortex-m0 is internal digital block
1. After synthesis, inout ports such as P0, P1, will be inferred as tri-state logic(TLAT). Is it ok? or please provide the recommanded method.
2. For scan chain insertion, additional independent input…

I'm trying to load the block diagram for the arty a7 M1 example project. I get this error:

[BD 41-1712] The specified IP 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'

Any thoughts on how to…