This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the ‘Want to maximise your product design? See how a custom ASIC can help?' webinar, view all the questions in the round-up blog post.

This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

Hi,

I am just performing the first steps with the DesignStart Eval Edition (Cortex-M0), trying to compile the verilog sources to get a simulation running.

So I changed /systems/fpga_testbench/trl_sim/makefile to use gcc and modelsim and now I want to …

Hi,

I'd like to try and use external BRAM as the I/D memory for the Cortex-M1 DesignStart package for Xilinx FPGAs. The reference examples for Arty boards use the internal TCMs.

I've built a design in Vivado with a BRAM connected to the AXI3 port mapped…

Hello all,

I have 2 questions regarding the Cortex M IP cores for Xilinx FPGAs (M1 on the Arty A7/S7, provided by ARM)

1) I am new to ARM DesignStart and am looking to use freeRTOS with the Cortex M1 which project which has been provided for the Arty A7…

Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error…

Hello,

I have already played around with the Cortex-M1 reference designs for Xilinx Spartan and Artix boards, can you give an indication of what your maximum target frequency for the processor IP core is? Are the referenced 100 MHz a good design practice…

I'm trying to load the block diagram for the arty a7 M1 example project. I get this error:

[BD 41-1712] The specified IP 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'

Any thoughts on how to…