• Cortex M7 cache ECC error

    David
    David

    Hi, 

    I'm currently working on STM32H7 which run a cortex M7. I'm trying to figure out how an ECC error upon a look up in the instruction or data cache is reported to the core. The only mention I've found, is in the Cortex-M7 reference manual as follow…

    • 1 month ago
    • Processors
    • Cortex-M / M-Profile forum
  • arm_mat_inverse_f32 producing incorrect singularities

    patrickrossiter
    patrickrossiter

    Hi there,

    I am trying to invert a matrix using arm_mat_inverse_f32(). I am getting correct results for some martices, but in the code below status3 = ARM_MATH_SINGULAR. status1 and 2 = ARM_MATH_SUCCESS.

    Any ideas what is wrong here? Note that det(m3) = -921600…

    • 3 months ago
    • Software Tools
    • Keil forum
  • Why the address of fuction printed is not same as the one mentioned in map file

    Gopu
    Gopu

    In Cortex-M7,Why the address of fuction printed is not same as the one mentioned in map file.

    i.e, My function address is 0x00473dbc in map fle, but it is diffrent, if we print it in my program.

        

    • 3 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • M7 to NIC-400 connectivity via AXIM

    Ramaswamy Vishwanath
    Ramaswamy Vishwanath

    AXIM bus from M7 has additional signals. How does NIC-400 convert this to AXI4 protocol

    • 3 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M7 SPI Interface Register Base Address

    atlasium47
    atlasium47

    Hello,

    I am trying to use the SPI interface on the Teensy 4.0 board which has a Cortex M7.  I found the registers and there offsets in the RM0444 Reference Manual but can't find the Base Address of these registers anywhere!

    Thanks

    • Answered
    • 4 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Booting of cortex M7 core, independently of cortex A53 core

    AnuragDoshi
    AnuragDoshi

    I have a development board of NXP that has 4 x A53 cores and 1 x M7 core. I want to run 2 different OSes on the boards that are independent of each other. And my goal is to boot the processors separately without having dependence of the other core for…

    • 6 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • SVCall returning to 0xdeadbeee

    DanS
    DanS

    Hi,

    I am developing for an ARM Cortex-M7 core (NXP iMIMXRT1062 chip), which is a Thumb only processor. I am using MCUXpressoIDE 11.1 which is based on Eclipse.

    I have a problem returning from SVCall. When free running, it usually ends up at address 0xdeadbeee…

    • 6 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Understanding interrupt latency and jitter in Cortex-M

    Simen Sørensen
    Simen Sørensen

    Hi,

    I've been trying to get a good grasp of the variables associated with interrupt handling in the Cortex-M family. I've read "A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the Arm Cortex-M processors" and "…

    • Answered
    • 7 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Reading suggestions to start programming with STM32H747 like mcu, especially with GCC

    Carlos Delfino
    Carlos Delfino

    I'm starting my studies on programming for Single Chip MCU with multicore, and I'm having a little trouble finding material on this topic.

    I read a post here in the community about the NXP's LPC4300 which is a Cortex-M4 + M0, which was very instructive…

    • 7 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Unexpected MPU fault

    Twoism
    Twoism

    Hello,
    I'm facing an unexpected issue while configuring the MPU on a Cortex-M7 (STM32H7). Basically, after setting the MPU in privileged thread mode, the execution continues up to when I switch to unprivileged thread mode writing into the CONTROL register…

    • 9 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • CPU cycle random changing

    User1988
    User1988

    Hello, i have an issue that seems to be from the compiler but i am not 100% sure. First of all the project was not made by me, but the company i work bought it from another company. As this project is related to a company i am not able to share many specific…

    • 9 months ago
    • Software Tools
    • Keil forum
  • STM32H745 dual-core debugging with IAR toolchain

    madhan719
    madhan719

    Hi All!

     

    I am working on STM32H745 dual-core controller and IAR Embedded Workbench for ARM toolchain V8.40.1 for development.

    I have completed all my work on individual core test and debugging with help of ST-Link V3 as debugger but unfortunately, I am…

    • 9 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Is there any extra parameter needed to start networking on FVP_MPS2_M7 simulator?

    shitaljadhav
    shitaljadhav
    • Hi,

    I need to publish a payload from mbed-os to MQTT broker. I am using FVP_MPS2_M7 as target, code is getting compiled but while running it on simulator(FVP_MPS2_Cortex-M7.exe) am getting an error code -3001 but when I use FVP_MPS2_M3 as target and…

    • 10 months ago
    • System
    • Embedded forum
  • Is M3 DesignStart similar to M7 Design Kit? (I don't yet have M7 Design Kit)

    MikeBoston
    MikeBoston

    Just starting... Is it reasonable to work through M3 DesignStart as an intro to M7 Design Kit?  (I do not yet have access to M7 Design Kit, but want to get a head start on my ARM project) I'm hoping that the ARM RTL, TB and other aspects of the supplies…

    • over 1 year ago
    • System
    • SoC Design forum
  • MPU config and memory attributes

    salar samani
    salar samani

    I want config STM32F746 MPU ,

    In the ARM Cortex M7 generic user guide External RAM memory region (0x60000000 - 0x7FFFFFFF)(512MByte) has WBWA (write back write allocate) cache policy see this link

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • STM32H7 CAN FD issues

    xolotl
    xolotl

    Hi everyone,

    I find myself working on a board with this microcontroller and I just have to get the CAN bus working.

    I have never done any programming with neither CAN or this micro.

    The issue I am encountering is this one:

    when I connect to the board…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cotex-M7 : Is there any hang case which TCMwait could make?

    kate mun
    kate mun

    Hello,

    I am using Cortex-M7 Processor and long latency memory with ITCM and DTCM

    I knew that TCM protocol defines multi-cycles TCMWAIT signal (I read Cortex-M7 TRM).

    So, I implemented ITCMWAIT and D#TCMWAIT.

    Now, I have the serious problem.

              The problem…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • SRAM reading problem using FMC at STM32H743.

    GlebK
    GlebK

    Hello.  I am trying to operate FMC interface in STM32H743 processor. Configuration was done using STM32cubeMX. 

    In code, after configuration, just have a loop with reading once per second.

    	      	  		HAL_SRAM_Read_8b(&hsram1, (uint32_t*)0x60000000, (uint8_t…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • COrtex M7 cache hit rate measurement

    kh1
    kh1

    Hello community,

    I have a Cortex M7 based product, and I want to measure the cache hit rate in different applications.compared to the cortex R5 the M7 does not embed a PMU.

     Do you have some idea on how to measure the cache hit rate in the ARM M7 core?

    …
    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Unable to determine offending instruction: usage fault illegal unaligned load or store cortex m7 keil mdk pro

    mzu2006
    mzu2006

    Problem

    Once in a blue moon (every ~500 hours of run time, non-deterministic) I am getting a Usage Fault/ Illegal unaligned load or store. Please, help me to trace the fault to actual offending instruction and extract additional info.

    What have I done…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Please assist with Usage Fault /Illegal unaligned load or store Cortex M7 Keil MDK-PRO

    mzu2006
    mzu2006

    Problem

    Once in a blue moon (every ~500 hours of run time, non-deterministic) I am getting a Usage Fault/ Illegal unaligned load or store. Please, help me to trace the fault to actual offending instruction and extract additional info.

    What have I done…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • "BX LR" causing INVPC Usage Fault exception

    Sohaib
    Sohaib

    I have implemented a context switching code. For going back to privileged user mode after setting the return value in SP + 0x18 address, I am using BX LR instruction.

    But code execution goes to HardFault handler and INVPC bit of USAFAULT register is set…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Suggestion on suitable arm processor

    Ma Seet Ting
    Ma Seet Ting

    Hi all. Nice to meet you all and glad that I have a chance to join this group=)
    Recently, I will do my final year project with the title of "Smart Home Control Using Brain Wave". Yet, I am not really sure on which arm that I should choose><…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • About FPU pipeline of Cortex-M7

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,


    The Cortex-M7 Lecture is opened on APS (ARM Partner Success) Site.
    Also, #4 and #5 are described the details of Cortex-M7 pipeline.
    However, I cannot understand the following parts of the lecture.
    Could anyone teach me them more clearly in…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M7 : Exception return query

    Ritesh Joshi
    Ritesh Joshi

    Hi I am working on Cortex M7. I am generating some interrupts and according to it my ISR is being called which I have already installed. After the execution of the ISR the PC is not returning to the instruction at the time of the interrupt, due to which…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
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