• Forced Hardfault (INVPC) Exception Error

    Lokesh
    Lokesh

    Using ARM coretx-M chip set

    Getting random  INVPC hard fault exception error, while running iperf tool for measuring n/w throughput.

    Hard fault reg: 0x40000000

    xPSR: 0x01000000

    PRIMASK: 0x00000001

    CONTROL: 0x00000000

    Please help to find the possible root…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • MFLOPS of M4F

    Timm Hinrichs
    Timm Hinrichs

    Hi,

    we are operating the M4F with 160MHz and we would like the know the MFLOPS we can achieve with this configuration.

    Regards,

    Timm

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    MSaif
    MSaif

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 - Returning from Interrupt

    marcusob
    marcusob

    Hi,

    I'm using the STM32 F407 (Cortex M4), and I am also only using assembly in uVision IDE. So far I have managed to setup a ISR for a pushbutton generated interrupt via GPIO. This all works, I get the ISR handler hit, but after I perform my ISR function…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cannot init heap using scatter file and C++ startup (Cortex-M4)

    Dron
    Dron

    Hello,

    I need help with heap initialization using scatter file and C++ startup.

    MCU is STM32F407VGT6 (Cortex-M4).

    Compiler is ARM Compiler 6.7, C++14.

    The problem is that all variables which I create dinamically on the heap have wrong addresses. My HEAP…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • M4 Assembly - Set Enable also enables the Clear Enable Interrupt Register

    marcusob
    marcusob

    Hi,

    I have some assembly for Cortex M4 (Arm 7M Thumb), I want to enable an interrupt that is connected to a push button on an STM32 F407. It works, but for some reason when I enable the set enable register, the clear enable register also gets set ? Is…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • what situation will the FPCA in Cortex-M4 change?

    ctc8631
    ctc8631

    Hi all,

    I'm study Cortex-M4 recently, and try to use floating point calculation,

    I read the book about that saying FPCA in control register will be set 1 after FPU work,

    but I'm not sure that when will FPCA be changed after set 1, or it will never…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Change Vector Table in cortex M4 in a persistent way

    EA8
    EA8

    Hello,

    I need to change the Vector Table but I need it to be persistent through a reset, what I'm trying to do is set a vector table duplicate as a safety measurement for reprogramming the original vector table.

    So far I being playing with the VTOR…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What happens to upper half of 32-bit data bus when reading 16-bit chip?

    Pszemol
    Pszemol

    Hi guys, I am interested in exploring a scenario when Cortex M4 cpu performs a 16-bit static memory read when 32-bit memory is actually on the board.

    The 16-bit memory chip is connected to lower half of the data bus, signals D0..D15 and there are two…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

    Trampas
    Trampas

    I have been reading through the ARM documentation on memory and instruction barriers. 

    I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

    I have also read the same about…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Interruptible Instructions on Cortex-M4

    praffeck
    praffeck

    The ARM Cortex-M4 Processor Technical Reference Manual states:

    To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Looking for typical max frequency for Cortex-M CPUs

    ahming
    ahming

    I'm looking for information on the typical max frequency (or typical frequency range) for the Cortex-M cores, in 40nm. Is there any documentation on that? Thanks.

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Raising priority of PendSV within NVIC when PendSV pending

    Ramzyo
    Ramzyo

    Hi,

    I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling with,

    1) High priority interrupt ISR is…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When an exception is taken into account

    Karolis
    Karolis

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • LDREX/STREX on the M3,M4,M7

    Trampas
    Trampas

    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex …

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to properly measure sleep time with DWT?

    Tilen
    Tilen

    Hello everyone,

    I need to measure sleep time of my Cortex-M4 processor (STM32F4xx).

    I looked at DWT where I also use normal tick counter and I enabled SLEEPCNT counter.

    However, I noticed that it is 8-bit register with event generation support.

    Now, there…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Prefetch Abort in Cortex M processors

    kmdinesh
    kmdinesh

    Hi,

    We are currently working with Cortex M4 processor and previously we worked with Cortex R5 processor. As part of our project requirement, we need to detect "prefetch abort" exception and to identify the corresponding address. In Cortex R5, we are taking…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Measuring Cortex-M4 instruction clock cycle counts

    Dan Lewis
    Dan Lewis

    I'm trying to find a reliable method for measuring instruction clock cycles on the STM32F429 MCU that incorporates a Cortex-M4 processor. Part of the challenge is that although the core CPU has no cache, ST added their own proprietary ART Accelerator…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • A panic function to halt the processor in low-power sleep using WFI?

    Alexei
    Alexei

    As part of fault detection / debugging, it's useful to have a panic() function that halts the processor.

    It is easy enough to disable interrupts and put the processor in an infinite busy loop (while (1)). However, that burns power, and I am looking…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • DWT

    Gabor M.
    Gabor M.

    Hello,

    I use DWT in Cortex-M4 to catch instructions that write or read memory contents and the problem is it doesn't stop immediately where I expect, it stops after 2-3 instruction later than where it should and the contents of registers are overwritten…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M register RAM and Flash periodical check?

    Half past nine
    Half past nine

    Hi ARM,

    How to check Cortex-M4 register,RAM and Flash periodically using software when the processor is running?

    Best regards,

    Frank

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Machine Learning: PlatformIO and CMSIS-NN

    RajeshSiraskar
    RajeshSiraskar

    Hi,

    I am trying to get started with Machine Learning and the ARM Cortex-M4 processors.

    I've been struggling to get started with neural-networks to work with the PlatformIO environment

    Does anyone here have experience with that please?

    Rajesh

    • over 1 year ago
    • Open Source Software and Platforms
    • Machine Learning forum
  • V2M MPS2+: 'ERROR: FPGA did not configure.'

    Riako
    Riako

    Hi all,

    We have purchased an MPS2+ platform, and everything was going well, but since Friday we are facing an error we do not understand.

    When starting the FPGA configuration (by pressing the 'ON' button on the board), leds start blinking (the screen…

    • Answered
    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • Which ARM development board should I use for audio DSP with ARM Cortex-M4?

    1370
    1370

    Hi experts.

    I am somehow new in ARM. Can anybody pls help me on choosing an appropriate cheap board for learning DSP with ARM cortex-M4?

    • over 2 years ago
    • Open Source Software and Platforms
    • Arm Development Platforms forum
  • CMSIS DSP stage_rfft_f32 function

    lukasz139
    lukasz139

    Hi,

    I am exploring the CMSIS DSP library. After playing for a while I have 2 questions:

    -in case I want to evaluate DFT over bigger data window than 4096 I would need to provide Twiddle Coefficient array for particular size and make aplit the data set…

    • over 2 years ago
    • Software Tools
    • Keil forum
<>