• Question about bit-banding for Tiva M4 core

    Robert
    Robert

    Hi,

    I read example projects of Tiva-C 1294. There are many similar uses '    GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_2, GPIO_PIN_2);'

    The prototype is :

    extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val)…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • M4/M0 dual core application. M0 fails to start

    Bo Mellberg
    Bo Mellberg

    Hello everyone,

    I have an LPC4337 running uCLinux. I'm trying to get code to run in the M0 in parallell.

    I load the code to 0x10080000, set the M0APPMEMMAP to 0x10080000, release the M0APP Reset and nothing happens. I have to reset the M0-core using…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • "Dormant Mode" for Cortex M3/M4

    Steven Dennis
    Steven Dennis

    Hi,

    We are interested in minimizing startup time from deep sleep mode.

    Some of the older ARM cores implement a dormant mode whereby the CPU core context (state) is written to RAM prior powering it down, and then then restored after the CPU core  is powered…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problem running copied code into flash

    Luís Rafael dos Santos Afonso
    Luís Rafael dos Santos Afonso

    Hi everyone,

    So I have a question.

    I have a ARM-M4 and for what I can tell this has both ARM and Thumb assembly. Meaning sometimes it interprets a 32 bit instruction as 2 16bit ones, some of the times.

    How does that work? How does it know how to go about…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Can anyone tell me where I can download the latest Cortex M4 Technical Reference Manual

    Peter Grey
    Peter Grey

    Where are the Technical Reference manuals located?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Do ARM processors have power good signal to check quality of incoming power?

    nirmalaranawat
    nirmalaranawat

    I am working on one of TI's SOC using ARM M-4 processor. I was wondering if the ARM processors have any Power Good signal which can be used in software stack to control flow of application.

    Or storing some data before power goes out completely.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does anyone use assembler only with an ARM MCU?

    Peter Grey
    Peter Grey

    I have only used assembler when working with MCU's. I can follow a C program but have not used it in any commercial product. Can anyone suggest a development platform to start off learning the ARM and C? I would probably work on a Cortex M4F as a start…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • about tail chaning of Cortex-M0

    下田敏郎
    下田敏郎

    Hello.

    I'm studying about the tail chaining of Cortex-M0.

    Is it same as Cortex-M3 or M4?

    Best regards.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Bit-banding in SRAM region (Cortex-M4)

    Matic
    Matic

    Hi.

    I would like to use bit-banding feature in SRAM, but don't know exactly how to implement it with C. I already use bit-banding in peripheral region with this kind of macro:

    #define BITBAND_PERI_REF        0x40000000…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARM CM4 FPU execption

    Anuj
    Anuj

    I am looking for FPU exception generation code. If some one share, or suggest some document for the same.

    Regards

    Anuj

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • cmsis NVIC question.

    Setianian
    Setianian

    Hello, Everybody. I have several questions.

    1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

    2. I would like…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Race condition between wake up event and WFI on Cortex-M3/M4

    neo
    neo

    When I read below thread in arm forum, I still not clear which one is the safety way.

    Cortex-M4: guaranteed wakeup from WFI?

    There're two solutions mentioned above, using WFE instead of WFI, and swap __WFI() and __enable_irq().

    I can understand WFE…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Process ADC data, moved by DMA, using CMSIS DSP: what's the right way?

    Andrea Bettati
    Andrea Bettati

    Hi to you all,
    I've a firmware running on a NXP LPCLink2 (LPC4370: 204 Mhz Cortex M4 MCU) board which basically does this:

    • Fills the ADC FIFO @40msps.
    • Copies the data into memory using the built-in DMA Controller and 2 linked buffers.
    • Processes one buffer…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Parallelism between CPU and FPU

    Matic
    Matic

    Hi.

    I have a question regarding Cortex-M4 processor with floating point unit. Is it somehow possible to do some computation in parallel in CPU (with integers) and FPU (with floats)?

    Probably not, because both units need their own instructions to perform…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • VTOR: offset address configuration

    Katsuhiro Atsumi
    Katsuhiro Atsumi

    Core: Cortex-M4F

    Do I need to configure vector table offset address to 0xnnnn_n000?

    In case of 0x3080(Flash region), the program jump to unexpected code.

    I think it is caused by mismatching between vector number and handler address.

    In case of 0x3000(Flash…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Usefulness of MPU in a non-OS system

    Matic
    Matic

    Hi.

    We are developing a product which has to achieve some safety requirements. The system is quite simple, non-OS, running in a Privileged mode only on a Cortex-M4. I would like to implement a Memory Protection Unit somehow. Could you please give any advice…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Memory protection unit - Cortex-M4

    Matic
    Matic

    Hi.

    I am writing back regarding MPU usage. I implemented it into the software in next ways (note, that program is quite simple - only privileged mode, no RTOS):

    1. I enabled background region, thus all addressable memory is fully accessible, unless there…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • vfp problem

    Ching Hsiung Yu
    Ching Hsiung Yu

    Hi

    I had a problem.

    I can use vfp in user mode but not work in priviledge level.

    Is there any wrong setting in CP10 , CP11 or any other wrong setting??

    BR

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 exception return sequence

    Gopal Amlekar
    Gopal Amlekar

    Hi,

    I think I am just getting confused with this even if (or because of) I read the book and manuals again and again.

    At exception entry, the processor saves R0-R3, R12, LR, PC and PSR on the stack. Saving PC means that the address of the instruction to…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How long bitfields on which ARM?

    Øyvind Teig
    Øyvind Teig

    I need to be able to handle long bitfields as effectively as possible. Right now I need up to 64 bits in length.

    Are there instructions to set, clear and test individual bits in one cycle available for some of the architectures? Which? Particularly, will…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Help me jump into ARM world !(I know nothing but AVR)

    kamran
    kamran

    Hi,  Sorry if this is a long thread but i'm really confused.

    I program for AVR MCUs and also know about Arduino, I can program for different ATMEL MCUs with looking at datasheets, And i also programmed a few basic stuff on Cortex-M3 LPC1768, without…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • serial wire debug

    harshan
    harshan

    sir,

         I am working with SWD(serial wire debug protocol) on cortex m4 architecture, one thing  i don't understand that i am unable to write value into registers r13 and r14 the remaining registers all are updating but for r13 and r14 i am unable to…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • updating CPSR in USER UNPRIVILEGED mode

    anoop
    anoop

    as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is user mode, since user mode is unpriviliged so i must…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Indication to begin a program

    amrani joutei
    amrani joutei

    I need some indications to begin writing a program.

    Write a compare routine to compare 64-bits values , using only two instructions.

    Thanks for your indications !

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M7 "zero overhead loop"

    Ari Mendes
    Ari Mendes

    Hi.

    In the page 22 of the document below informs that the cortex-m7 has "zero overhead loops" capability. I would like to know how it is done? Is there a special instruction for it?

    http://community.arm.com/servlet/JiveServlet/downloadBody/9595…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
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