• Cortex M0+, AHB state during Exception

    mjkhtx
    mjkhtx

    I have a STM32L031 (Cortex M0+).

    I need to ensure that the SRAM is not modified externally by the DMA during a (very short) cyclic SRAM test.

    My first thought was to force an Exception, block the AHB, do the test and return. A short delay will not cause…

    • Answered
    • 4 months ago
    • Processors
    • Cortex-M / M-Profile forum