Our team has developed a custom SoC with embedded flash blocks and a Cortex M0. Given that the code flash download routine will have to be customized, I am looking for some help and information on how to get started. The SoC as a 2 wire SWD interface…

Unlike the Design kit makefiles, in which tool-chain (Keil, DS5 or GCC) can be chosen, the Prototyping kit makefiles uses only DS5.

Is it possible to receive Prototyping kit makefiles that support tool-chain selection and in particular GCC?

This question was raised in the webinar "Enhance your product with industry-leading processors - for no upfront license fee.”

Hi,

I am using the MPS2+ board to debug my DesignStart Cortex-M0. The core is up and running and now I want to program the onboard SRAM. On the SDCard I can see that \MB\HBIO263C\AN387\images.txt expects an axf file.

Is it possible to generate an .axf…

Hi,

II refer to the example MCU system level in the document "arm_cortex_m0_designstart_eval_user_guide", put it into MPS2+ after synthesis, the software uses the following example in this directory.

D:\CMPS3\AT510-MN-80001-r2p0-00rel0\systems…

We are using Cortex-M0 DesignStart Pro to design MCU. When we use SWD to download grogram to flash in FPGA(Cortex_m0 mcu inside),  we cannot to connect keil with FPGA, and Keil shows:" Could not stop Cortex-M device!Please check the JTAG cable. "…

Hi,

I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.

And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using…