Hello Guys!
I am Integrating Cortex-M0 with peripherals and memories. Previously I used Block ROM/RAM in FPGA where I just uploaded COE files to make it run. But now I want to use an external flash to do the Job. I have the following questions which I…
Our team has developed a custom SoC with embedded flash blocks and a Cortex M0. Given that the code flash download routine will have to be customized, I am looking for some help and information on how to get started. The SoC as a 2 wire SWD interface…
There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg
niallcooling's Developing a Generic Hard Fault handler for Armv7-M
also:
For the last weeks, I have been trying to get this new version to work. I did the same as with the previous version and now it is running on the Xilinx Nexys4. However, honestly I do not have any idea how to get the debugging to work. I defined the pins…
